As design rule continues to shrink, resolution enhancement techniques (RET) such as optical proximity correction (OPC) become more and more complex to enable design printability. As we know, typically integrated circuit (IC) layouts are simple shapes such as rectangles. However, high spatial frequency components of the mask spectrum that are not captured by the low-pass pupil result in a rounded image. In addition, the diffusion process in the postexposure bake (PEB) step makes the wafer rounding effects worse. This means that it is difficult to get the wafer image to match the design exactly at corners, even with the most aggressive OPC methodology. Therefore, pre-OPC site placement optimization is necessary to achieve high quality wafer images. In this work, a contour-based OPC methodology is proposed to minimize the time consumption in pre-OPC simulation site placement optimization and OPC job running. Rounded target contours that best describe the real intended wafer result are used as the target during OPC correction. By comparing classical OPC recipe-driven target point placement and contour-based OPC methodology, it is found that contour-based OPC methodology can achieve comparable image quality in a shorter turn around time (TAT) with fewer engineer resources.
Traditional double-exposure lithography (DEL) or double-patterning lithography (DPL) methodologies stem most from the resolution enhancement standpoint. A single mask with high feature densities is split into two exposure steps, each with lower feature densities that can be easily resolved. The DEL is proposed as the process window enhancement technology for sub-110-nm technology. Features with sparse pitches are printed by a first step of dense pitch exposures and a second exposure with dummy features removed. The pattern decomposition strategy described is similar to that of subresolution assisting features (SRAF). So it is compatible with the traditional rule-based SRAF implementation methodology. By comparing the depth of focus (DOF) of the 110-nm lithography process between the single exposure and the double exposure, it is found that the DOF for marginal features is extended by using double-exposure methodology, and thus extends the capability of KrF exposure tools. Furthermore, the link between the overlay performance and the overlap of the second exposure's trim slots over the first exposure is studied. The results show that the overlay control is within the KrF scanner capability. As a further study, the proposed double-exposure methodology for the 90-nm lithography process is evaluated.
In the past several years, DFM (design for manufacturability) is widely used in semiconductor process. DFM is
to make layout design optimized for manufacturability's sake. Lithography friendly design (LFD) is one branch of DFM.
To enhance process margin of photolithography, layout designers typically modify their layout design with the
application of DFM or LFD tools. Despites those application, it is still not enough to realize enough process window as
technology node goes to beyond 45nm. For these reasons, OPC (Optical proximity correction) engineers apply
additional layout treatment prior to applying OPC. That is called as table-driven retarget, which is typically conducted by
rule-based table. Similar to rule-based OPC, table-driven retarget also has limitations in its application.
In this paper, we presented a model-based retargeting method to overcome the limitation of table-driven retarget.
Once the criteria of process window has been set, we let OPC tool simulate the process window of each layout of design
firstly. Then, if the output value of the simulated result cannot meet the preset criteria, OPC tool resizes the layout
dimension automatically. OPC tool will do retarget-OPC-retarget iterations until process windows of all of designs
become within the criteria. After all, the model-based retarget can guarantee accurate retarget and avoid over or under
retarget in order to improve process window of full chip design.
Rule-based fragmentation has been used for many years in Optical Proximity
Correction (OPC). It breaks the edge of polygons into small pieces according to the
pre-defined rule based on the topography and context before model-based OPC.
Although it works well in most case, it can not place the fragment point onto the
proper position which decided by inherent Optical and process requirement
In this paper, an adaptive fragmentation is proposed. The polygon is first dissected
according to the traditional rule. In the following iteration, the edge is re-fragmented,
in which some fragments are deleted and some new fragments are created, according
to their image properties. Using this method, the dissection point can be placed in the
right position. It can improve the correction accuracy and eliminate the unwanted
fragment at the same time.
Due to the corner rounding effect in litho process, it is hard to make the wafer image as sharp as the
drawn layout near two-dimensional pattern in IC design<sup>1, 2</sup>. The inevitable gap between the design and
the wafer image make the two-dimensional pattern correction complex and sensitive to the OPC
correction recipe. However, there are lots of different two-dimensional patterns, for example, concave
corner, convex corner, jog, line-end and space-end. Especially for Metal layer, there are lots of jogs are
created by the rule-based OPC. So OPC recipe developers have to spend lots to efforts to handle
different two-dimensional fragment with their own experience.
In this paper, a general method is proposed to simplify the correction of two-dimensional structures.
The design is firstly smoothed and then simulation sites are move from the drawn layer to this new
layer. It means that the smoothed layer is used as OPC target instead of the drawn Manhattan pattern.
Using this method, the OPC recipe tuning becomes easier. In addition, the convergence of
two-dimensional pattern is also improved thus the runtime is reduced.
Various resolution enhancement techniques have been proposed in order to enable optical lithography
at low k1 imaging, e.g. alt-PSM (phase shift mask), chromeless phase lithography (CPL), double
exposure technique (DET) and double dipole lithography (DDL). In spite of its low throughput in
production, DDL technique is a very attractive solution for low k1 process because of the relatively low
cost of binary or attenuated phase shift masks, which can be combined with strong dipole illuminations
and flexible SRAF rule to enhance the process window. Another attraction of DDL is that dry scanner
still can be used for 45nm node instead of expensive immersion lithography process.
In this paper, two aspects for DDL application have been focused on. The first one is OPC optimization
method for DDL, which includes SRAF optimization, mask decomposition and pixel-based OPC. The
whole flow is optimized specifically for DDL to achieve satisfactory pattern results on wafer. The
second is the overlay issue. Since two DDL masks are exposed in turn, the overlay variation between
two masks becomes dominant factor deteriorating pattern quality. The effect of overlay tolerance is also
studied through process window simulation.
DDL has been demonstrated to be capable of 45nm node logic with dry scanner. The pattern fidelity and
process window of 45nm node SRAM & Random Logic are evaluated for active/gate layer and dark
field metal layer.