A high-speed double delta sampling (DDS) circuit with pipelined structure for CMOS image sensor (CIS) is presented. Considering the low readout speed of the DDS circuit compare with correcting double sampling (CDS) circuit, We separate the main operation of DDS circuit into two steps, and run the two steps alternately in odd readout column and even readout column, which seems like the pipelined operation. Thus, the readout speed of the DDS will as twice as fast than the traditional DDS. The architecture and readout sequence of the new circuit are introduced in detail. Meanwhile simulation results indicate the proposed circuit can achieve a high speed performance.