Electrostatic discharge (ESD) problem resulting from charges on wafers is a serious concern in IC manufacturing. As is discovered in our paper, three types of defect, AA (active area) damage, IMD (Inter Metal Dielectric) crack and Via hole W corrosion that are confirmed to be induced by lithography process related ESD charging effect. We carefully studied the mechanism of these ESD charging effect by DOE splits and succeeded to dig out that these electric charge major comes from the lithography develop process. In the lithography coating and developing wafer process, the wafer will be at high spin speed at many of the steps which will easy help to store the electric charge on the wafer. In our study, the rinse step in developing process is the most key factor to store the electric charge on wafer. In generally, the higher rinse speed, the higher positive electric charge. Furthermore, we also discovered that the different step in develop rinse process have different impact on charge level, in which the acceleration and deceleration step has the highest charge voltage.
As to minimize and eliminate the ESD damage in lithography process, we finally carry out the simplified recipe optimization solution which only need optimize for the develop rinse speed with different in-coming surface charge level and process application, so that can be easy implemented in the worldwide fabs.
Photo resist micro bubble and void defect is reported as a typical and very puzzle defect type in photo lithography process, it becomes more and more significantly and severely with the IC technology drive towards 2× node. Introduced in this paper, we have studied the mechanism of photo resist micro bubble at different in-coming wafer surface condition and tested a series of pre treatment optimization method to resolve photo resist micro bubble defect on different wafer substrate, including in the standard flat and smooth wafer surface and also in special wafer surface with high density line/space micro-structure substrate as is in logic process FinFET tri-gate structure and Nor type flash memory cell area Floating Gate/ONO/Control Gate structure. As is discovered in our paper, in general flat and smooth wafer surface, the photo resist micro bubble is formed during resist RRC coating process (resist reduction coating) and will easy lead to Si concave defect after etch; while in the high density line/space micro-structure substrate as FinFET tri-gate, the photo resist void defect is always formed after lithography pattern formation and will final cause the gate line broken after the etching process or localized over dose effect at Ion IMP layers. The 2nd type of photo resist micro bubble is much more complicated and hard to be eliminated. We try to figure out the interfacial mechanism between different type of photo resist (ArF, KrF and I-line) and pre-wet solvent by systematic methods and DOE splits. And finally, we succeeded to dig out the best solution to eliminate the micro bubble defect in different wafer surface condition and implement in the photolithography process.