In recent technology nodes, advanced process and novel integration scheme have challenged the precision limits of conventional metrology; with critical dimensions (CD) of device reduce to sub-nanometer region. Optical metrology has proved its capability to precisely detect intricate details on the complex structures, however, conventional RCWA-based (rigorous coupled wave analysis) scatterometry has the limitations of long time-to-results and lack of flexibility to adapt to wide process variations. Signal Response Metrology (SRM) is a new metrology technique targeted to alleviate the consumption of engineering and computation resources by eliminating geometric/dispersion modeling and spectral simulation from the workflow. This is achieved by directly correlating the spectra acquired from a set of wafers with known process variations encoded. In SPIE 2015, we presented the results of SRM application in lithography metrology and control , accomplished the mission of setting up a new measurement recipe of focus/dose monitoring in hours. This work will demonstrate our recent field exploration of SRM implementation in 20nm technology and beyond, including focus metrology for scanner control; post etch geometric profile measurement, and actual device profile metrology.
Traditional metrology solutions face a range of challenges at the 1X node such as three dimensional (3D) measurement capabilities, shrinking overlay and critical dimension (CD) error budgets driven by multi-patterning and via in trench CD measurements. With advent of advanced technology nodes and 3D processing, an increasing need is emerging for in-die metrology including across-structure and structure-to-structure characterization. A myriad of work has emerged in the past few years intending to address these challenges from various aspects; in-die OCD with reduced spot size and tilt beam on traditional critical dimension scanning electron microscopy (CDSEM) for height measurements. This paper explores the latest capability offered by PeakForceTM Tapping Atomic Force Microscopy (PFT-AFM).
The use of traditional harmonic tapping mode for scanning high aspect ratio, and complex “3D” wafer structures, results in limited depth probing capability as well as excessive tip wear. These limitations arise due to the large tip-sample interaction volume in such confined spaces. PeakForce Tapping eliminates these limitations through direct real time control of the tip-sample interaction contact force. The ability of PeakForce to measure, and respond directly to tip- sample interaction forces results in more detailed feature resolution, reduced tip wear, and improved depth capability. In this work, the PFT-AFM tool was applied for multiple applications, including the 14nm fin and replacement metal gate (RMG) applications outlined below. Results from DOE wafers, detailed measurement precision studies and correlation to reference metrology are presented for validation of this methodology.
With the fin application, precision of 0.3nm is demonstrated by measuring 5 dies with 10 consecutive runs. Capability to resolve within-die and localized within-macro height variation is also demonstrated. Results obtained from the fin measurements support the increasing trend that measurements in the scribe line may not accurately represent in-die geometry, thus indicating the increasing need to measure the real device area.
In-die measurement capability of peak force tapping AFM on wafers at post-poly-removal step in the RMG module is also evaluated. Precision of 1.22nm for the fin height under the gate, 1.06nm for the total gate height, and 0.77nm for the overburden are achieved in this application on a semidense structure. To the knowledge of the authors, this is the first demonstration of a robust in-die measurement of the fin height under the gate.
The line edge roughness (LER) and line width roughness (LWR) transfer in a self-aligned quadruple patterning (SAQP) process is shown for the first time. Three LER characterization methods, including conventional standard deviation method, power spectral density (PSD) method and frequency domain 3-sigma method, are used in the analysis. The wiggling is also quantitatively characterized for each SAQP step with a wiggling factor. This work will benefit both process optimization and process monitoring.
Proc. SPIE. 9424, Metrology, Inspection, and Process Control for Microlithography XXIX
KEYWORDS: Metrology, Image segmentation, Atomic force microscopy, Optical testing, Scanning electron microscopy, 3D metrology, Critical dimension metrology, Semiconducting wafers, Overlay metrology, Back end of line
Traditional metrology solutions are facing a range of challenges at the 1X node such as three dimensional (3D) measurement capabilities, shrinking overlay and critical dimension (CD) error budgets driven by multi-patterning and via in trench CD measurements. Hybrid metrology offers promising new capabilities to address some of these challenges but it will take some time before fully realized. This paper explores new capabilities currently offered on the in-line Critical Dimension Scanning Electron Microscope (CD-SEM) to address these challenges and enable the CD-SEM to move beyond measuring bottom CD using top down imaging.
Device performance is strongly correlated with Fin geometry causing an urgent need for 3D measurements. New beam tilting capabilities enhance the ability to make 3D measurements in the front-end-of-line (FEOL) of the metal gate FinFET process in manufacturing. We explore these new capabilities for measuring Fin height and build upon the work communicated last year at SPIE1. Furthermore, we extend the application of the tilt beam to the back-end-of-line (BEOL) trench depth measurement and demonstrate its capability in production targeting replacement of the existing Atomic Force Microscope (AFM) measurements by including the height measurement in the existing CDSEM recipe to reduce fab cycle time.
In the BEOL, another increasingly challenging measurement for the traditional CD-SEM is the bottom CD of the self-aligned via (SAV) in a trench first via last (TFVL) process. Due to the extremely high aspect ratio of the structure secondary electron (SE) collection from the via bottom is significantly reduced requiring the use of backscatter electrons (BSE) to increase the relevant image quality. Even with this solution, the resulting images are difficult to measure with advanced technology nodes. We explore new methods to increase measurement robustness and combine this with novel segmentation-based measurement algorithm generated specifically for BSE images. The results will be contrasted with data from previously used methods to quantify the improvement. We also compare the results to electrical test data to evaluate and quantify the measurement performance improvements.
Lastly, according to International Technology Roadmap for Semiconductors (ITRS) from 2013, the overlay 3 sigma requirement will be 3.3 nm in 2015 and 2.9 nm in 2016. Advanced lithography requires overlay measurement in die on features resembling the device geometry. However, current optical overlay measurement is performed in the scribe line on large targets due to optical diffraction limit. In some cases, this limits the usefulness of the measurement since it does not represent the true behavior of the device. We explore using high voltage imaging to help address this urgent need. Novel CD-SEM based overlay targets that optimize the restrictions of process geometry and SEM technique were designed and spread out across the die. Measurements are done on these new targets both after photolithography and etch. Correlation is drawn between the two measurements. These results will also be compared to conventional optical overlay measurement approaches and we will discuss the possibility of using this capability in high volume manufacturing.
At 1× node, a three-dimensional (3-D) FinFET process raises a number of new metrology challenges for process control, including gate height and fin height. At present, there is a metrology gap in inline in-die measurement of these parameters. To fill this metrology gap, in-column beam tilt has been implemented on Applied Materials V4i+ critical dimension scanning electron microscope for height measurement. Low-tilt (5 deg) and high-tilt (14 deg) beam angles have been calibrated to obtain the height and the sidewall angle information. Evaluation of its feasibility and production worthiness is done with applications in both gate height and fin height measurements. Transmission electron microscope correlation with an R2 equal to 0.89 and a precision of 0.81 nm have been achieved on various in-die features in a gate height application. The initial fin height measurement shows less accuracy (R2 being 0.77) and precision (1.49 nm) due to greater challenges brought by the fin profile, yet it is promising for the first attempt. Sensitivity to design of experiment offset die-to-die and in-die variations is demonstrated in both gate height and fin height. The process defect is successfully captured with inline gate height measurement. This is the first successful demonstration of inline in-die gate height measurement for a 14-nm FinFET process control.
At 1X node, 3D FinFETS raise a number of new metrology challenges. Gate height and fin height are two of the most important parameters for process control. At present there is a metrology gap in inline in-die measurement of these parameters. In order to fill this metrology gap, in-column beam tilt has been developed and implemented on Applied Materials V4i+ top-down CD-SEM for height measurement. A low tilt (5°) beam and a high tilt (14°) beam have been calibrated to obtain two sets of images providing measurement of sidewall edge width to calculate height in the host. Evaluations are done with applications in both gate height and fin height. TEM correlation with R2 being 0.89 and precision of 0.81nm have been achieved on various in-die features in gate height application. Fin height measurement shows less accuracy (R2 being 0.77) and precision (1.49 nm) due to challenges brought by fin geometry, yet still promising as first attempt. Sensitivity to DOE offset, die-to-die and in-die variation is demonstrated in both gate height and fin height. Process defect is successfully captured from inline wafers with gate height measurement implemented in production. This is the first successful demonstration of inline in-die gate height measurement for 14nm FinFET process control.