In this paper, we present the approach and results of layer-aware source mask target optimization. In this approach, the design target is co-optimized during source mask optimization (SMO) by considering inter-layer constraints. We tested the method on a 2x nm node metal layer by using both standard and customized cost functions for source optimization. Variable targets were defined for two process window limiting critical pattern cells, with contact-to-metal and metal-tovia coverage rules taken into consideration. The results indicate that layer-aware source mask target optimization gives consistent process window improvement over conventional SMO. The optimized targets prove to be a good balance between lithography process window and post-etch inter-layer coverage margin.
A cost-efficient technique for full-chip source and mask optimization is proposed in this paper. This technique has two
components: SMO source optimization for full-chip and flexible mask optimization (FMO). During the technology
development stage of source optimization, a novel pattern-selection technique was used to identify critical clips from a
full-set of design clips; SMO was then used to optimize the source based on those selected critical-clips. This pattern-selection
technique enables reasonable SMO runtime to optimize the source that covers the full range of patterns. During
the process development stage and product tapeout stage, FMO is employed. The FMO framework allows the use of
different OPC computational techniques on different chip areas that have different sensitivities to process variations.
Advanced OPC methods are applied only where they are needed, therefore achieving optimum process performance with
the least tapeout and mask cost.