Turbo codes are now universally known as one of the most effective techniques for achieving performance very close to the Shannon theoretical limits in many transmission systems. This paper presents a speed optimized ASIC turbo decoder core's design. The proposed architectures achieve a complexity reduction. Because of the recursion algorithm, the result of recursion is used immediately in following cycle. A reasonable pipeline is adopted by averaged the critical path to eliminate this effect. Core is fit to realize not only in FPGA, but also can embedded into other DSP and the decode rate can reach 6 Mbps in 0.18 um technology.
KEYWORDS: Signal to noise ratio, Digital signal processing, Data compression, Clocks, Data storage, Field programmable gate arrays, Computer programming, Telecommunications, Signal processing, Wireless communications
Due to their near Shannon-capacity performance, turbo codes have received a considerable amount of attention since their introduction. They are particularly attractive for cellular communication systems and have been included in the specifications for both the WCDMA(UMTS) and cdma2000 third-generation cellular standards. The log-MAP decoding algorithm and some technologies used to reduce the complexity have discussed in the past days. But we can see that if we apply the Turbo code to wireless communications,the decoding process rate is the bottleneck. The software implement is not realistic in today’s DSP process rate. So the hardware design is supposed to realize the decoding. The purpose of this paper is to present a full ASIC design way of Turbo decoding. Many technologies are added to the basic Log-MAP algorithm to simple the design and improve the performance. With the log-MAP algorithm, the Jacobi logarithm is computed exactly using max*()=ln(exp(x)+exp(y))=max()+fc(|y-x|),The correction function fc(|y-x|) is important because there will be 0.5dB SNR loss without it. The linear approximation can be used and the linear parameters was selected carefully to suit hardware realize in our design. In order to save the power consumption and also to assure the performance, the quantization is important in ASIC design, we adopt a compromise scheme to save the power and also there is good BER behaves. Many noisy frames can be corrected with a few iterations while some of the more noisy frames need to experience a full number of iterations (NOI). Thus, if the decoder could stop the iteration as soon as the frame becomes correct, the average NOI would be reduced. There are many ways to stop the iteration such as CRC, compare and so on, we adopt a significantly less computation and much less storage stop criteria. For long frames the memory for storing the entire frame of the forward probability α or the backward probability β can be very large. Available products all use sliding-window version of the turbo decoder to reduce the memory requirements. This is also true in our design. In addition of this, a new method is adopted to expand the sliding window length but without increasing the storing requirement. This method also improves the performance evidently.
The technologies adoped in the paper are suited hardware design for wireless application. For example, this decoding core can be embedded into our 32-bit digital signal processor (MD-32) to realize 3G basestation receiver.