The next generation beyond 7nm node potentially requires the implementation of Sub-Resolution Assist Features (SRAF) with EUV lithography. This paper aims at providing a clear SRAF strategy for the next generation beyond 7nm node designs through a series of experiments. Various factors are considered, including: stochastic effects, 3D mask effects, through-slit effects, aberrations, and pixelated SMO sources.
EUV has 13.5nm as its wavelength, which is much smaller than the wavelength used in ArF lithography, and this gives very different imaging challenges compared to the ArF case. Due to the small wavelength and numerical aperture (NA) of the current EUV tools, depth of focus is not as significant of a concern as in DUV. Instead, EUV lithography is severely challenged by stochastic effects, which are directly linked to the slope of the intensity curve. DUV SRAF has been shown to be a powerful tool for improving NILS/ILS, as well as DOF, and here we explore how that translates into EUV imaging. In this paper, we consider Process Variability (PV) Bands with a variety of process conditions including focus/dose/mask bias changes and also the NILS/ILS as our objective functions, to determine what the best SRAF solution is for a set of test patterns. We have full investigations on both symmetric SRAF and asymmetric SRAF.
SRAF can potentially mitigate image shift through focus, i.e. non-telecentricity, caused by EUV 3D shadowing effect. This shadowing effect is pattern dependent and contributes to the overlay variation. As we approach the next generation beyond 7nm node, this image shift can be more significant relative to the overlay budget, hence we further investigate the impact of SRAF placement to the image shift. Moreover, the Center of Focus shift due to the large 3D mask absorber thickness can be potentially mitigated by SRAF implementation. The common process window is significantly impacted by both the center of focus shift and the individual depth of focus. We study the change by adding SRAF using both a symmetric source (standard source) and an asymmetric source (SMO source). Once SRAF is inserted for the test patterns, the common process window is plotted to compare the solutions with and without SRAF.
Finally, we understand the importance of using full flare map and full through slit model (including aberration variation through slit) in the main feature correction, but in this paper, we will further evaluate the need of using full models in SRAF insertion. This is a necessary step to determine the strategy of SRAF implementation for the next generation beyond 7nm node.
Process window OPC (PWOPC) is widely used in advanced technology nodes as one of the most important resolution enhancement techniques (RET).1 PWOPC needs to consider not only edge placement error (EPE) from nominal condition simulations, but also constraints based on process variation simulations, such as pinch and bridge related requirements based on process variation band (PVBAND). Those constraints can be challenging to meet as feature size continues to shrink in advanced nodes.
In this paper a novel matrix retargeting based PWOPC was developed to find optimal OPC solutions by solving constraints-based matrix and applying minimal retargeting as needed.2 Experiment results showed enhanced process window and reasonable performance.
In this paper advanced OPC (Optical Proximity Correction) methods, additional with assistant features, and non-obvious
methods were implemented to correct aberrations caused by aggressive illuminations in order to optimize the shape of
the finger tips. OPC model and simulations were verified using 2D verification method.
A perspective is presented on how the semiconductor integrated circuit industry has evolved and what we can expect over the next decade or two. However, this 'forecast' is given in only the broadest sense, to make it relatively independent on innovations and discoveries that are likely to strongly shape the industry over this time period. Rather, trends are examined, as well as general 'tools' that will undoubtedly be important in advancing from our present microelectronics era to our presumable future in nanoelectronics.