Proc. SPIE. 5819, Digital Wireless Communications VII and Space Communication Technologies
KEYWORDS: Signal to noise ratio, Digital signal processing, Clocks, Optical spheres, Field programmable gate arrays, Computer simulations, Antennas, Algorithm development, Computer architecture, Prototyping
Multiple-input multiple-output wireless systems use multiple antennas in both transmitter and receiver. The huge capacity of this multi-environment system has attracted intensive interests in recent years. Hardware implementation of MIMO lattice decoder becomes a challenging task because of the complexity of the lattice decoding algorithms. This paper compares two typical lattice decoding algorithms in hardware implementations. The data dependency among the iterative closest lattice point search procedure is examined and the possibilities of parallel implementation are explored. Parallel architectures are designed for each algorithm and are prototyped on two different hardware platforms: FPGA and DSP. Decoding rate and bit error rate are compared between the two algorithms. The performance of different hardware platforms is investigated as well. The experimental results show that the FPGA-based AV algorithm decoder supports 17.6Mbit/s decoding rate when mapped on a Xilinx Virtex2 1000 FPGA, and is more than 7 times faster than the VB algorithm decoder on the same hardware. To achieve the compatible bit error rate performance, FPGA based lattice decoder provides an order of magnitude faster decoding rate than the DSP decoder using the same algorithm.
Proc. SPIE. 5819, Digital Wireless Communications VII and Space Communication Technologies
KEYWORDS: Signal to noise ratio, Digital signal processing, Clocks, Optical spheres, Field programmable gate arrays, Signal processing, Antennas, Algorithm development, Computer architecture, Prototyping
This paper presents the architecture design of a high data rate universal lattice decoder for MIMO channels on FPGA platform. A phost strategy based lattice decoding algorithm is modified in this paper to reduce the complexity of the closest lattice point search. The data dependency of the improved algorithm is examined and a parallel and pipeline architecture is developed with the iterative decoding function on FPGA and the division intensive channel matrix preprocessing on DSP. Simulation results demonstrate that the improved lattice decoding algorithm provides better bit error rate and less iteration number compared with the original algorithm. The system prototype of the decoder shows that it supports data rate up to 7Mbit/s on a Virtex2-1000 FPGA, which is about 8 times faster than the original algorithm on FPGA platform and two-orders of magnitude better than its implementation on a DSP platform.
While most of the routing protocols of wireless sensor networks try to minimize the energy consumptions to extend the system life-time, it is also critical to design a protocol that is scalable and fault-tolerant. In this paper, we introduce a clusterhead multihop routing algorithm for meshed wireless sensor networks. Each identified junction node in the mesh network is selected as a clusterhead. The routing decisions are only made at the clusterheads. A simplified link-state routing algorithm is used to find the shortest routing path among all available clusterheads in the network. This algorithm exploits the feasibility and fault tolerance of routing protocol, while coping with the severe energy constraint and the requirement for network scalability. Time division multiple access technique is employed in the medium access control layer for further reduction of energy consumption. Multiple-level cluster hierarchy approach is also discussed for more complicated meshed sensor networks.
Wireless sensor networks have become a viable solution to automating and enhancing some applications. One such application is monitoring street lamps in a city. This paper introduces a routing algorithm for sensors attached to street lamps on the roads of the city. Since this network will reside along man-made roads, the physical layout of the network is restricted and static. In general, the algorithm routes packets from junction to junction until the packet reaches the intended street/avenue. Once the packet reaches the street/avenue on which the destination lies, the nodes route the packet in the direction of the specific destination node. The three main goals of this algorithm are fault-tolerance, reliability, and minimal energy. The results of two test scenarios are presented for a faultless network and a faulty network respectively. For faultless networks, the algorithm was able to achieve near-optimal routing paths from source nodes to destination nodes. In addition, the algorithm is adaptive and robust enough to insure packet delivery to its destination in marginally faulty networks. Hence, the results show that this algorithm is close to fulfilling all three of these goals.
Wireless sensor networks provide an opportunity of innovations while also brings unique challenges. Collaborations between sensor nodes are generally required for complicated applications. As a key component for node collaboration, robust routing protocols that are able to effectively communicate among multiple nodes become necessary. In wireless sensor networks, these protocols are energy efficient and provide low latency. In this paper, we develop optimal distance geographic routing (ODGR), an application-independent protocol using power control in the transmission scheme and the available geographic information to dynamically explore the optimal routing path in order to reduce the total transmission energy and routing latency. ODGR is built on the optimal distance theory derived exclusively from the fundamental transmission energy model. Detail procedures of ODGR are presented for practical implementations. Case study of a two-dimensional mesh network shows that ODGR is able to reduce total transmission energy by 66.41% and 43.89%, and average latency by 76.45% and 26.27% respectively compared to traditional MTE and cluster algorithms, thus ODGR can improve the system-life and the performance of wireless sensor networks.
Wireless sensor network has attracted considerable research attention as the world becomes more information oriented. This technology provides an opportunity of innovations in traditional industries. Management and control of streetlight system is a labor-intensive high-cost task for public facility operations. This paper applies wireless sensor network technology in streetlight monitoring and control. Wireless sensor networks are employed to replace traditional physical patrol maintenance and manual switching on every lamp in the street or along the highway at the aim of reducing the maintenance and management expense. Active control is used to preserve energy cost while ensuring public safety. A proof-of-concept network architecture operated at 900 MHz industrial, scientific, and medical (ISM) band is designed for a two-way wireless telemetry system in streetlight remote control and monitoring. The radio architecture, multi-hop protocol and system interface are discussed in detail. MOTES sensor nodes are used in simulation and experimental tests. Simulation results show that the sensor network approach provides an efficient solution to monitor and control lighting infrastructures through wireless links. The unique application in this paper addresses an immediate need in streetlight control and monitoring, the architecture developed in this research could also serve as a platform for many other applications and researches in wireless sensor network.
Proc. SPIE. 5438, Visual Information Processing XIII
KEYWORDS: Signal to noise ratio, Image processing, Digital filtering, Interference (communication), Field programmable gate arrays, Telecommunications, Signal processing, Image filtering, Electronic filtering, Filtering (signal processing)
Image noise cancellation is necessary to remove noise generated in communication systems or remote video conferencing systems. Processing speed has become a challenge as a consequence of the increasing image resolution, especially in visual information processing. This paper presents the design and implementation of a real-time image noise canceller. Two-dimensional least mean square (TDLMS) algorithm is employed as the adaptive filter for noise cancellation. This algorithm is modified and designed with two concurrent phases: filter coefficient adjustment phase and image noise cancellation phase, with each phase mapping into a pipeline structure, therefore achieving real-time performance. The image noise canceller is implemented using hardware description language VHDL and is prototyped on Field Programmable Gate Array (FPGA) for system reconfiguration. A data buffer is developed using SelectRAM (BRAM) embedded in a Virtex FPGA to overcome the bandwidth limitation between external memory and the noise cancellation processor. The FPGA embedded multipliers are also employed to improve the processing speed. Tested using standard images, this real-time image noise canceller could process up to 1528 frames of 256 by 256 pixel images per second and could reach up to 10.4dB signal to noise ration improvement.
Multiphysics system involves the interaction of different processes, including electrical, mechanical, and chemical processes. Modeling a multiphysics system is a complicated task. A physically-based modeling technique starts with a set of governing differential equations. Analytic solution is hard to achieve, and numerical simulation generally requires intensive computation power and excessive execution time. A general purpose processor is unable to satisfy both the performance and the speed requirement. This paper presents a FPGA-based architecture that could speed up multiphysics system modeling in an order of one to two magnitudes. Hardware architectures for equations used to modeling both linear and nonlinear systems are presented, which provide an FPGA-based platform where multiple equations can perform integration simultaneously in a collaborative mode. This new methodology utilizes both parallel and pipeline mechanisms of the FPGA to accelerate complex system simulation. The performance of the FPGA-based architectures is tested using the initial value problem case studies. The implementation results show that the FPGA-based computing engine provides satisfactory computation accuracy, fast implementation speed, and affordable low cost.