The DSP blocks on modern FPGAs are highly capable and support a variety of different multiplication operation. High level synthesis is one of the important DSP block development tools. the tool needs accurate estimation latency of the DSP block application circuit in order to produce good design solutions while converts the C++ code to Verilog code. Especially DSP blocks have pipeline structure, the latency estimation is more important. We propose a machine learning method which can accurate estimation minimum latency of DSP block multiplication application circuit in high level synthesis. The experiments show that the proposed approach is more accurate than Vivado-Hls to estimate the latency of DSP block application circuit. Sometimes the same clock frequency, using the method of this paper, the DSP application circuit can save 50% latency than the Vivado HLS tool.
With the increase of FPGA (Field Programmable Gate Array, FPGA) functionality, FPGA has become an on-chip system platform. Due to increase the complexity of FPGA, estimating the delay of FPGA is a very challenge work. To solve the problems, we propose a transfer learning estimation delay (TLED) method to simplify the delay estimation of different speed grade FPGA. In fact, the same style different speed grade FPGA comes from the same process and layout. The delay has some correlation among different speed grade FPGA. Therefore, one kind of speed grade FPGA is chosen as a basic training sample in this paper. Other training samples of different speed grade can get from the basic training samples through of transfer learning. At the same time, we also select a few target FPGA samples as training samples. A general predictive model is trained by these samples. Thus one kind of estimation model is used to estimate different speed grade FPGA circuit delay. The framework of TRED includes three phases: 1) Building a basic circuit delay library which includes multipliers, adders, shifters, and so on. These circuits are used to train and build the predictive model. 2) By contrasting experiments among different algorithms, the forest random algorithm is selected to train predictive model. 3) The target circuit delay is predicted by the predictive model. <p> </p>The Artix-7, Kintex-7, and Virtex-7 are selected to do experiments. Each of them includes -1, -2, -2l, and -3 different speed grade. The experiments show the delay estimation accuracy score is more than 92% with the TLED method. This result shows that the TLED method is a feasible delay assessment method, especially in the high-level synthesis stage of FPGA tool, which is an efficient and effective delay assessment method.