A phased array operates by modulating the phases of several signals, allowing electronic control over the locations that these signals interfere constructively or destructively, allowing the beam to be steered. A space-based laser phased array, called the Directed Energy System for Targeting of Asteroids and exploRation (DE-STAR) has previously been posited by our group for a number of uses, from planetary defense to relativistic propulsion of small probes. Here we propose using the same basic system topology as a receiver rather than a transmitter. All of the components in the system, excluding the laser, are bidirectional. Rather than each elements transmitting laser light, they would instead receive light, which will then be combined to create an interference pattern that can be imaged onto a focal plane. The Laser Array Space Telescope (LAST) uses most of the same components and metrology as DE-STAR and could thus be integrated into a singular system, allowing both transmit and receive modes. This paper discusses the possible applications of this system from laser communications to astrophysics.
In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features
must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum
coloring spacing.5, 11, 14 However, there exist pattern configurations for which pattern features separated by
less than the minimum coloring spacing cannot be assigned different colors. In such cases, DPL requires that
a layout feature be split into two parts. We address this problem using a layout decomposition algorithm that
incorporates integer linear programming (ILP), phase conflict detection (PCD), and node-deletion bipartization
(NDB) methods. We evaluate our approach on both real-world and artificially generated testcases in 45nm
technology. Experimental results show that our proposed layout decomposition method effectively decomposes
given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design
rule violations in the final decomposed layout. While we have previously reported other facets of our research
on DPL pattern decomposition,6 the present paper differs from that work in the following key respects: (1)
instead of detecting conflict cycles and splitting nodes in conflict cycles to achieve graph bipartization,6 we split
all nodes of the conflict graph at all feasible dividing points and then formulate a problem of bipartization by
ILP, PCD8 and NDB9 methods; and (2) instead of reporting unresolvable conflict cycles, we report the number
of deleted conflict edges to more accurately capture the needed design changes in the experimental results.
The aggressive scaling of VLSI feature size and the pervasive use of advanced reticle enhancement technologies
leads to dramatic increases in mask costs, pushing prototype and low volume production designs at the limit
of economic feasibility. Multiple project wafers (MPW), or "shuttle" runs, provide an attractive solution for
such designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs of the
same technology flow. However, delay cost associated with schedule alignment is ignored in previous work. The
saving on mask cost may be easily surpassed by the profit loss due to the schedule alignment. Therefore, Multi-
flow Multi-layer Multi-project Reticles (MFMLMPR) become a more viable mask-cost saving technique for low
volume production since it share the mask cost between different layers of the same design and between designs
of different technology flows. However, MFMLMPR design introduce complexities not encountered in traditional
single-flow or single-layer reticles.
In this paper we propose the first design flow for MFMLMPR aimed at minimizing the total manufacturing
cost (including mask cost, wafer cost and delay cost) to fulfill given die production volumes. Our flow includes
three main steps: (1) schedule-aware project partitioning with multi-flow embedding (2) multi-frame reticle
design, and (3) multi-project frame floorplanning. Our contributions are as follows. For the first step, a fast
iterative matching algorithm is proposed to calculate the mask cost for multi-flow embedding with consideration
of all practical manufacturing costs. We then propose an integer linear programming (ILP) based method for
optimal manufacturing cost minimization. Since ILP suffers from impractically long runtimes when the number
of projects is large, we propose a sliding time window heuristic to exhaustively search the solution space for the
best tradeoff between mask cost and delay cost. For the second step, we propose an ASAP frame embedding
heuristic to minimize the mask cost. Finally, a "generalized chessboard" floorplan with simulated annealing is
proposed to generate more dicing friendly frame floorplans for multi-flow projects, observing given maximum
We have tested our flow on production industry testcases. The experimental results show that our schedule-aware
project partitioner yields an average reduction of 58.4% in manufacturing cost. The reduction of mask cost
is around 46.3% compared with use of traditional layer-by layer checking methods. Our generalized chessboard
floorplanner leads to an average reduction of 22.8% in the required number of wafers compared to the previous
best reticle floorplanner.
As advanced technologies in wafer manufacturing push patterning processes toward lower-k1 subwavelength
printing, lithography for mass production potentially suffers from decreased patterning fidelity. This results in
generation of many hotspots, which are actual device patterns with relatively large CD and image errors with
respect to on-wafer targets. Hotspots can be formed under a variety of conditions such as the original design being
unfriendly to the RET that is applied, unanticipated pattern combinations in rule-based OPC, or inaccuracies
in model-based OPC. When these hotspots fall on locations that are critical to the electrical performance of
a device, device performance and parametric yield can be significantly degraded. Previous rule-based hotspot
detection methods suffer from long runtimes for complicated patterns. Also, the model generation process that
captures process variation within simulation-based approaches brings significant overheads in terms of validation,
measurement and parameter calibration.
In this paper, we first describe a novel detection algorithm for hotspots induced by lithographic uncertainty.
Our goal is to rapidly detect all lithographic hotspots without significant accuracy degradation. In other words,
we propose a filtering method: as long as there are no "false negatives", i.e., we successfully have a superset of
actual hotspots, then our method can dramatically reduce the layout area for golden hotspot analysis. The first
step of our hotspot detection algorithm is to build a layout graph which reflects pattern-related CD variation.
Given a layout L, the layout graph G = (V, Ec union Ep) consists of nodes V, corner edges Ec and proximity edges
Ep. A face in the layout graph includes several close features and the edges between them. Edge weight can be
calculated from a traditional 2-D model or a lookup table. We then apply a three-level hotspot detection: (1)
edge-level detection finds the hotspot caused by two close features or "L-shaped" features; (2) face-level detection
finds the pattern-related hotspots which span several close features; and (3) merged-face-level detection finds
hotspots with more complex patterns. To find the merged faces which capture the pattern-related hotspots,
we propose to convert the layout into a planar graph G. We then construct its dual graph GD and sort the
dual nodes according to their weights. We merge the sorted dual nodes (i.e., the faces in G) that share a given
feature, in sequence. We have tested our flow on several industry testcases. The experimental results show that
our method is promising: for a 90nm metal layer with 17 hotspots detected by commercial optical rule check
(ORC) tools, our method can detect all of them while the overall runtime improvement is more than 287X.
A well-known recipe for reducing mask cost component in product development is to place non-redundant elements of
layout databases related to multiple products on one reticle plate [1,2]. Such reticles are known as multi-product, multi-layer,
or, in general, multi-IP masks. The composition of the mask set should minimize not only the layout placement
cost, but also the cost of the manufacturing process, design flow setup, and product design and introduction to market.
An important factor is the quality check which should be expeditious and enable thorough visual verification to avoid
costly modifications once the data is transferred to the mask shop. In this work, in order to enable the layer placement
and quality check procedure, we proposed an algorithm where mask layers are first lined up according to the price and
field tone . Then, depending on the product die size, expected fab throughput, and scribeline requirements, the
subsequent product layers are placed on the masks with different grades. The actual reduction of this concept to practice
allowed us to understand the tradeoffs between the automation of layer placement and setup related constraints. For
example, the limited options of the numbers of layer per plate dictated by the die size and other design feedback, made
us consider layer pairing based not only on the final price of the mask set, but also on the cost of mask design and fab-friendliness.
We showed that it may be advantageous to introduce manual layer pairing to ensure that, e.g., all
interconnect layers would be placed on the same plate, allowing for easy and simultaneous design fixes. Another
enhancement was to allow some flexibility in mixing and matching of the layers such that non-critical ones requiring
low mask grade would be placed in a less restrictive way, to reduce the count of orphan layers. In summary, we created a
program to automatically propose and visualize shuttle mask architecture for design verification, with enhancements to
due to the actual application of the code.
The pervasive use of advanced reticle enhancement technologies demanded by VLSI technology scaling leads to dramatic increases in mask costs. In response to this trend, multiple project wafers (MPW) have been proposed as an effective technique for sharing the cost of mask tooling among up to tens of prototype and low volume designs. Previous works on MPW reticle design and dicing have focused on the simple scenario in which production volumes are known a priori. However, this scenario does not apply for low- and medium-volume production, in which mask manufacturing is typically started when only rough estimates of future customer demands are available. In this paper we initiate the study of MPW use for production under demand uncertainty and propose efficient algorithms for two main optimizations that arise in this context: reticle design under demand uncertainty and on-demand wafer dicing. Preliminary experiments on simulated data show that our methods help reducing the cost overheads incurred by demand uncertainty, yielding solutions with a cost close to that achievable when a priori knowledge of production volumes is available.
Increasing transistor densities, smaller feature sizes, and the aggressive use of RET techniques with each successive process generation have collectively presented new challenges for current fracture tools, which are at the heart of layout data preparation. One main challenge is to reduce the number of small dimension trapezoids (slivers) to improve mask yield since the sliver count reflects the risk of mask critical-dimension errors.
Some commercial tools are available for handling the sliver minimization problem in fracture, such as CATS from Synopsys and Fracturem from Mentor Graphics. However, the number of slivers in the existing fracture solutions can be significantly reduced. The integer linear programming (ILP) method has been previously applied to find the optimal fracture but has not explored potential benefits from additional ray-segments. Unfortunately, the ILP becomes prohibitively slow for polygons with the large number of vertices and heuristic partitioning of large polygons may severely degrade the solution quality.
In this paper, we propose a new ray-segment selection heuristic which can find a near-optimal fracture solution in practical time while being flexible enough to take into account all specified requirements. We fist divide the rectilinear region with all rays from the concave points and formulate the fracture problem as a sequential ray-segment selection problem. Each ray segment is assigned a weight based on its probability to form a sliver. All ray segments to be selected are placed in a candidate pool. An iterative "gain" based process is used for fast and efficient selecting ray segments from the candidate pool and dynamic update of ray segments and their gains. Further reduction of the number of slivers is achieved by auxiliary ray-segments. The resulted runtime overhead is reduced by a rule-based auxiliary ray-segments addition method which achieves a tradeoff between the sliver number reduction and runtime overhead. Compared with state-of-art sliver-driven fracturing tools, the proposed method reduces the number of slivers in the fractures of two industry testcases by 76.7% and 58.6%, respectively, without inflating the runtime and shot count. Similarly, compared with the previous ILP based fracture methods, the new method reduces the number of slivers by 56.1% and 2.2%, respectively, with more than 60X speedup and insignificant shot count overhead. The reduction in the sliver number is primarily due to the introduction of additional ray-segments. The proposed method can also solve the reverse-tone fracture problem in practical time for large industry testcases.
The aggressive scaling of VLSI feature size and the pervasive use
of advanced reticle enhancement technologies has lead to dramatic
increases in mask costs, pushing prototype and low volume production designs at the limit of economic feasibility. Multiple project wafers (MPW), or "shuttle" runs, provide an attractive solution for such low volume designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs. However, MPW reticle design and wafer dicing introduce complexities not encountered in typical, single-project wafers. Recent works on wafer dicing adopt some assumptions to reduce the problem complexity. Although using one or more assumptions makes the problem solvable, the feasibility or performance of the solutions may be degraded. Also, the delay cost associated with schedule alignment was ignored in all previous works. In this paper we propose a general MPW flow including four main steps: (1) schedule-aware project partitioning (2) multi-project
reticle floorplanning, (3) wafer shot-map definition, and (4) wafer dicing plan definition. Our project partitioner provides the best trade-off between the mask cost and delay cost. Our reticle floorplaner can automatically clone a design to better fit given
production volumes. The round wafer shot-map definition step allows extracting functional dies from partially printed reticle images. Finally, our dicing planner allows multiple side-to-side dicing plans for different wafers and image rows/columns within a wafer. Experiments on industry testcases show that our methods outperform significantly not only previous methods in the literature, but also reticle floorplans manually designed by experienced engineers.
Depth of focus is the major contributor to lithographic process margin. One of the major causes of focus variation is imperfect planarization of fabrication layers. Presently, OPC (Optical Proximity Correction) methods are oblivious to the predictable nature of focus variation arising from wafer topography. As a result, designers suffer from manufacturing yield loss, as well as loss of design quality through unnecessary guardbanding. In this work, we propose a novel flow and method to drive OPC with a topography map of the layout that is generated by CMP simulation. The wafer topography variations result in local defocus, which we explicitly model in our OPC insertion and verification flows. Our experimental validation uses 90nm foundry libraries and industry-strength OPC and scattering bar recipes. We find that the proposed topography-aware OPC can yield up to 90% reduction in edge placement errors at the cost of little increase in mask cost.
Mask manufacturing for the approaching 90nm and 65nm nodes increasingly deploys variable shaped beam (VSB) mask writing machines. This has led to high interest in the fracturing methods which are at the heart of layout data preparation for VSB mask writing. In this paper, we set out the main requirements for fracturing and suggest a new solution approach based on integer linear programming (ILP). The main advantage of the new method is that the ILP finds optimal solutions while being flexible enough to take into account all specified requirements. We also suggest several decomposition (polygon partitioning) heuristics which speed up the ILP approach. Experimental comparisons with leading industry tools show significant improvement in quality, as well as acceptable scalability, of the proposed methods. In particular, our fracturing solutions reduce shot count (which reflects write time and mask cost) and dramatically reduce sliver count (which reflects the risk of mask critical-dimension errors). Our results reveal significant headroom that can be exploited by future design-to-mask tools to reduce the manufacturing variability and cost of IC designs.