Advanced process control loop for SAQP pitch walk with combined lithography, deposition and etch actuators
Edge placement error fundamentals and impact of EUV: will traditional design-rule calculations work in the era of EUV?
EPE fundamentals and impact of EUV: Will traditional design-rule calculations work in the era of EUV?
EUV mask flatness compensation strategies and requirements for reticle flatness, scanner optimization and E-beam writer (Conference Presentation)
Minimizing wafer overlay errors due to EUV mask non-flatness and thickness variations for N7 production