A high-speed flexible transistor made with an ultrapure carbon nanotube (CNT) solution is reported. The carrier transport layer of the CNT-based flexible transistor is formed at room temperature by dispensing a tiny droplet of an electronics-grade CNT solution. Ultra high field-effect mobility of ~ 48,000 cm2/(V×s) has been demonstrated on a thin-film field effect transistor (TFT). A simple trans-impedance voltage follower circuit was made using the CNT-TFT on a transparency film. The circuit exhibited a high modulation speed of 312 MHz and a large current-carrying capacity beyond 20 mA. The transparency and the sheet resistance of the CNT-film were also characterized at different wavelengths. The ink-jet printing-compatible process would enable mass production of large-area electronic circuits on virtually any desired flexible substrate at low cost and high throughput.
Carbon nanotubes (CNTs) are of great interests for a wide range of applications because of their unique structural,
mechanical, electrical, optical, thermal, and chemical properties. Particularly, CNT thin films can be used as
mechanically flexible, electrically conductive, and broadband optically transparent electrodes in various optoelectronic
devices. However, one crucial obstacle to implementing CNT-based applications has been the unavailability of pure
CNTs suitable for direct industrial use. The as-produced CNTs are very fluffy soot, and thus extremely difficult to be
handled in the device fabrication process. Although CNTs can be grown directly on a substrate from the catalyst
deposited on the substrate surface, the growing temperature is very high, typically > 900°C, which represents a big
challenge to device fabrication and integration. Another issue is that the catalyst on the substrate surface must be
removed without affecting the grown CNTs. In the raw CNT soot, there is always a considerable amount of impurities,
including metallic particles from the catalyst and carbonaceous impurities from the chemical reaction by-products. Such
impurities can greatly degrade the properties of CNT thin films. The production of electronic-grade CNT aqueous
solutions, which contain only individually suspended pure CNTs without any kind of surfactant, is a critical milestone
for implementing CNT-based applications. By using such solutions, pure CNT thin films of various densities can be
formed through common solution-casting processes, such as spin coating, spray coating, micro-dispensing, and ink-jet
printing. The properties of these pure CNT thin films will be discussed in this paper.
A printable high-speed flexible electronics based on ultrapure carbon nanotube (CNT)
solution is reported. The carrier transport layer of the CNT-flexible electronics is formed
at room temperature by dispensing a tiny droplet of an electronic-grade CNT solution that
does not contain any surfactant. This CNT-TFT exhibited a high modulation speed of 312
MHz and a large current-carrying capacity beyond 20 mA. The carrier transport layer of
the CNT-flexible electronics also show a high transparency of over 90% in the longwave
infrared (LWIR) region. Such IR-transparent electronics are of great importance for a
great variety of applications including IR-transparent smart-skins, IR-invisible antennas,
and embedded IR-sensing, imaging and communications. The ink-jet printing compatible
process would enable mass production of large-area electronic circuits on virtually any
desired flexible substrate at low cost and high throughput.
A 3-slot optical backplane bus demonstrator based on glass substrate with photopolymer volume gratings array (PVGA)
on top surface is built to allow 16 channels of data to be broadcast from central slot to two daughter slots or uploaded from
any daughter slot to central slot. VCSELs and photodetectors packaged in the form of TO-46 can are assembled on top of
each PVG and interleaved to reduce the crosstalk to below noise level. By carefully aligning the fabrication system, the
incident angle deviation from Bragg condition is reduced to below 0.1° to maximize optical power delivery. The
orientation and period of hologram fringes are uniform in the active area by collimating recording beams.
Above 4.8Gbps aggregated data transmission is successfully demonstrated using the multi-channel system. Three
computer mother boards using FPGA are made to verify the data transmission among the slots. Interface boards between
the FPGA boards and optical transceivers are designed and fabricated to separate the implementation of digital layer and
optical layer. Single channel transmissions with 3.2Gbps and even 10Gbps data rate are also tested with above 100uW
input power, showing the potential to improve the total two-way bandwidth to above 102.4Gbps. Alignment tolerance of
the optical interconnect system is investigated theoretically and experimentally. By analyzing the diffractive
characteristics, the bandwidth limit of the optical layer is determined to be in the order of Terahertz. Design and
fabrication issues are discussed for future optical backplane bus to make terahertz bandwidth into reality. Based on the
experiments for Bit-interleaved Optical Backplane bus and Multi-channel optical backplane bus demonstrators,
theoretical analysis of the bandwidth limit of the optical backplane bus using photopolymer volume gratings has been
Optical backplane bus based on glass substrate with volume holographic gratings on top surface possesses a great ability to broadcast information. This feature is utilized to accomplish a bit-interleaved optical interconnect system. In this system, each daughter board sends only one bit per round and the bit pulses from different boards can cascade in a designed series when the transmitters are distributed in an appropriate manner. In this way, even slow electronic chips can be coordinated to generate an aggregate bandwidth up to 10Gbps, which is impossible to achieve with a multi-drop electrical bus. Besides the benefits of high data rate and low crosstalk, such a bit-interleaved architecture provides a secure data storage method. Each daughter board only stores a quarter bits of any byte, so that no single board has the entire information and security is enhanced. Alignment tolerance and power budget of the proposed optical interconnect system is theoretically calculated and experimentally verified. With collimating lenses, the packing density of transceivers is more than 4/cm2, and thus the signal density can be above 40Gbps/cm2/board. The insertion loss due to misalignment and beam divergence is measured to be approximately 3dB. The bit error rate (BER) of 10Gbps receivers with -12dBm sensitivity is estimated to be below 10-12.
As multiprocessing comes into the mainstream, the board-to-board interconnects become even more critical. In a shared-memory multiprocessing system, the shared bus topology is the preferred interconnect scheme because its broadcast nature can be effectively utilized to reduce communication latency, lessen networking complexity, and support cache coherence. In the electrical domain, however, a major performance bottleneck is anticipated due to the restricted bus bandwidth. In this paper, an innovative architecture, optical centralized shared bus, is proposed for use in the multiprocessing systems. This architecture utilizes the terascale bandwidth capacity of substrate-guided optical interconnects, while at the same time, retaining the essential merits of the shared bus topology. Thus, a smooth migration with substantial multiprocessing performance improvement is expected. A conceptual emulation of the shared-memory multiprocessing scheme is demonstrated on a generic PCI subsystem with an optical centralized shared bus. The objective of this effort is to prove the technical feasibility from the architecture standpoint.
With the ever-increasing need to solve larger and more complex problems, multiprocessing is attracting more and more research efforts. One of the challenges facing the multiprocessor designers is to fulfill in an effective manner the communications among the processes running in parallel on multiple multiprocessors. The conventional electrical backplane bus provides narrow bandwidth as restricted by the physical limitations of electrical interconnects. In the electrical domain, in order to operate at high frequency, the backplane topology has been changed from the simple shared bus to the complicated switched medium. However, the switched medium is an indirect network. It cannot support multicast/broadcast as effectively as the shared bus. Besides the additional latency of going through the intermediate switching nodes, signal routing introduces substantial delay and considerable system complexity. Alternatively, optics has been well known for its interconnect capability. Therefore, it has become imperative to investigate how to improve multiprocessing performance by utilizing optical interconnects. From the implementation standpoint, the existing optical technologies still cannot fulfill the intelligent functions that a switch fabric should provide as effectively as their electronic counterparts. Thus, an innovative optical technology that can provide sufficient bandwidth capacity, while at the same time, retaining the essential merits of the shared bus topology, is highly desirable for the multiprocessing performance improvement. In this paper, the optical centralized shared bus is proposed for use in the multiprocessing systems. This novel optical interconnect architecture not only utilizes the beneficial characteristics of optics, but also retains the desirable properties of the shared bus topology. Meanwhile, from the architecture standpoint, it fits well in the centralized shared-memory multiprocessing scheme. Therefore, a smooth migration with substantial multiprocessing performance improvement is expected. To prove the technical feasibility from the architecture standpoint, a conceptual emulation of the centralized shared-memory multiprocessing scheme is demonstrated on a generic PCI subsystem with an optical centralized shared bus.
With the increasing demand for solving more complex problems, high-performance multiprocessing systems are attracting more and more research efforts. One of the challenges is to effectively support the communications among the processes running in parallel on the multiprocessors. Due to the physical limitations of electrical interconnects, interconnection networks impose a potential bottleneck limiting the overall performance. On the other hand, optics has many advantages as an interconnect technology. In this paper, benefits of optics are evaluated along with a comparison of two mainstream system topologies, shared bus and switched media. This analysis leads to an innovative interconnect architecture, optical centralized shared bus. The crucial design aspects of this architecture, including system organization, working principle, and conversion between free-space propagation and substrate-guided mode propagation by using volume holographic gratings, are delineated. To ensure the feasibility of using this architecture as high performance interconnection networks in real multiprocessing systems, a PCI implementation of the centralized shared memory multiprocessor system is proposed. In this prototype, the required connectivity is accomplished by using the optical centralized shared bus architecture. Some preliminary results are presented.
We describe a new method for broadcasting signals in an optical backplane bus system based on guided-wave interconnects. By introducing a distributor (an active coupler) in the center board, which consists of a receiver, a doubly multiplexed hologram, and a transmitter, all signals coming from boards are collected in a receiver in the distributor and then are rebroadcasted from transmitter in the distributor to all boards. This method shows a variety of advantages such as equalized fan-out powers, increased the interconnect distance, reduced number of holograms, and easier system assembly. We show the design concepts for a centralized optical backplane, and resulting experimental performance advantages over previously- developed free-space and guided-wave optical backplane bus systems.
We design and implement a system demonstrator based on vertical-cavity surface-emitting lasers, polymeric hologram grating couplers, and metal-semiconductor-metal photodetectors. As a preliminary experiment, we show the feasibility of board-to-board level substrate-guided wave optoelectronic interconnections in the real electrical system. First, we introduce a new architecture--centralized optical backplane--for board-to-board level interconnections. Second, the optoelectronic data channel is constructed compatible with standard PECL and capable of operating a 1.25 Gbps. Finally, it is employed to replace the conventional electrical data channel in a microprocessor system. We describe the performance of the entire system and discuss the future application of our centralized optical backplane in other electrical systems.