Double-patterning ArF immersion lithography continues to advance the patterning resolution and overlay requirements and has enabled the continuation of semiconductor bit-scaling. Over the years Lithography Engineers continue to focus on CD control, overlay and process capability to meet current node requirements for yield and device performance. Reducing or eliminating variability in any process will have significant impact, but the sources of variability in any lithography process are many. The goal from the light source manufacturer is to further enable capability and reduce variation through a number of parameters. <p> </p>Recent improvements in bandwidth control have been realized in the XLR platform with Cymer’s DynaPulse<sup>TM</sup> control technology. This reduction in bandwidth variation could translate in the further reduction of CD variation in device structures. The Authors will discuss the impact that these improvements in bandwidth control have on advanced lithography applications. This can translate to improved CD control and higher wafer yields. A simulation study investigates the impact of bandwidth on contrast sensitive device layers such as contacts and 1x metal layers. Furthermore, the Authors will discuss the impact on process window through pitch and the overlapping process window through pitch that has been investigated. These improvements will be further quantified by the analysis of statistical bandwidth variation and the impact on CD.
We describe design house approaches for design rule developments with emphasis of valuations of pre-optical proximity correction (pre-OPC) layouts and their simulation results. To begin, we describe the procedure of the simulation model calibration. An evaluation of metrics for analyzing the design layouts is then described. Due to the unavailability of post-OPC layouts, both pre-OPC and trial-OPC simulations are studied. A range of layout pattern density, within which the pre-OPC metric follows the post-OPC's, is estimated. Within this pattern density range, pre-OPC layout then can be evaluated to identify potential process "hot spots." With this approach, a set of design for manufacturability (DFM) compliance design rules is derived and applied to the product developments for both 90- and 65-nm process technology nodes. Several hot spots in the products (designed with 90-nm design rules) are located and fixed using layout optimization guided by the DFM rules. Simulated image contours and in-line scanning electron microscope (SEM) images validate the approach.
As semiconductor process technology moves to 65nm and beyond, RET (resolution enhancement technology)
becomes more and more important, especially in low k1 processes, where it is used frequently.
Currently, in the 65nm generation, the k1 is ~0.4 on a 0.85 NA exposure tool. However, the NA improvement of the
exposure tool cannot meet the schedule of generation movement very well. Low k1 technology must be applied on next
generation processes. For the 45nm generation, a 0.93 NA exposure tool is available currently and is used to achieve the
production criteria. Because the k1 value is quite low (~0.31), using traditional methods cannot satisfy process
For metal layers of the 45nm generation, 55nm photo-resist CD (critical dimension) patterning of 130nm pitch is a
difficult goal on a 0.93 NA exposure tool. Traditional OAI (off-axis-llumination) (annular mode) cannot provide enough
image contrast for pattern printing. Customization of illumination mode is an approach on low k1 processes. Another one
is utilizing light source polarization to achieve resolution improvement. In this paper, we introduce different approaches
on 45nm metal patterning. The RET approach (C-quad. illumination mode with polarization) can provide enough image
contrast in pattern printing to solve process issues.
As the advent of advanced process technology such as 90-nm and below, the design rules become more and more complicated than before. These complicated design rules can guarantee process margin for the most layout environments. However, some layouts have narrow process windows that were still within the design rules. For example, line end layouts in a dense environment would generally have narrower process window than that of the onedimensional (1-D) dense line environment. The dense line end spacing design rule would be larger than that of the 1-D dense line spacing to compensate for the narrow window effect. In this work, an optical simulation software was used to examine an existing 90-nm FPGA product pre-OPC layout for its optical contrast. The optical contrast could correlate to the depth of focus (DOF) process window. Several back end locations were identified with possible narrow DOF windows. From the evaluations of these low contrast patterns, several design for manufacturing (DFM) rules and DRC deck was then developed. This deck
effectively identified the narrow process window layout locations, previously found with the simulation software. These locations were then optimized for the improved DOF windows. Both simulation and in-line data showed that the DOF window was improved after the layout optimization. Product data with optimized layouts also showed the improved yield.