Proc. SPIE. 8005, MIPPR 2011: Parallel Processing of Images and Optimization and Medical Imaging Processing
KEYWORDS: Digital signal processing, Image compression, Digital image processing, Detection and tracking algorithms, Image processing, Field programmable gate arrays, Signal processing, Very large scale integration, Automatic target recognition, Binary data
A special designed VLSI chip for template matching fundamentally used in automatic target recognition is proposed in
this paper, it adopts normalized cross correlation algorithm. Parallelism inherent in the operation is explored to reduce
the huge needed external bandwidth. As much as 8 large binary templates could be configured into four operation modes
of eight 1-bit, four 2-bit, two 4-bit and one 8-bit templates using partial product scheme and they are processed in
parallel. It takes 13.23ms to execute 120x160 template matching with 256x320 image, therefore is suitable for
real-time applications. The prototype of the chip is emulated on FPGA and also synthesized with Design Compiler, die
area is 3mm x 3.1mm and power consumption is 114.1 mw when operate at 108 MHz.
Scene-based adaptive non-uniformity correction (NUC) of Infrared Focal Plane Array (IRFPA) has been a key
technology. However, all the scene-based correction methods require that the objects be in the state of motion. Once
objects that don't move enough tend to be "melt" into the background, the target fade-out and ghost artifacts will occur in
the corrected image. On the other hand, although some scene-based algorithms eliminate the non-uniformity effectively,
the computations are complicated, and so it is difficult to be implemented by VLSI technique. In this work we propose a
new adaptive algorithm based on motion information and the steep descent method. The simulation shows that the new
algorithm has inhibited target fade-out and eliminated the ghost artifacts effectively. As the proposed algorithm
characterized by inherent parallelism, modularity and regularity, we also propose its parallel VLSI architecture and
implement it using 0.18μm CMOS technology.
In this paper, we proposed a new way of implementing non-uniformity correction (NUC) techniques by using NVIDIA
CUDA parallel programming model. Non-uniformity and bad cells problems generally exist in Infrared Focal Plane
Array (IRFPA) Sensors and real-time correction is needed before further processing. With the intrinsic parallel nature of
most non-uniformity correction algorithms, the ever popular multi-core multi-thread processor architecture is a suitable
match. We'll investigate several non-uniformity correction techniques on CUDA, CPU and ASIC platforms and compare
the results in processing power, latency, costs and etc.