Intel has reported on three separate styles and applications of strong phase shift masks (PSMs) over the last decade
including alt-PSM for gate patterning, alt-PSM with assist features for contact patterning and Pixelated Phase Masks
(PPMs) for metal layer patterning. Each had a prominent role in Intel's Design For Manufacturing (DFM) infrastructure development in terms of design rules and DFM tooling. By gradually inserting design rule changes for alt-PSM for gate patterning starting from the 130nm technology node, density and design impact were minimally effected.
Alt-PSM for contact layer required development of complex methods of SRAF placement and coloring while also
forcing advances in phase shift mask manufacturing infrastructure. Pixelated phase masks for metal patterning when
combined with Inverse Lithography Techniques (ILTs) were successful in supporting a high level of flexibility for metal
design rules including multiple feature sizes, pitches and two-dimension content.
We present a simple reaction rate analysis of lithographic patterning using the Non-Reciprocal Photo Base Generation
(NRPBG) scheme of Bristol (Bristol, et. al., to be published in Proceedings of the SPIE - The International Society for
Optical Engineering, 2010, presentation 7639-4). Multistep reaction kinetics simulations demonstrate that the NRPBG
scheme produces clear pitch division upon 193 nm double-exposure, over a range of photochemical reaction rate
We present the results of both theoretical and experimental investigations of materials for application either as a
reversible Contrast Enhancement Layer (rCEL) or a Two-Stage PAG. The purpose of these materials is to enable Litho-
Litho-Etch (LLE) patterning for Pitch Division (PD) at the 16nm logic node (2013 Manufacturing). For the rCEL, we
find from modeling using an E-M solver that such a material must posses a bleaching capability equivalent to a Dill A
parameter of greater than 100. This is at least a factor of ten greater than that achieved so far at 193nm by any usable
organic material we have tested.
In the case of the Two-Stage PAG, analytical and lithographic modeling yields a usable material process window, in
terms of reversibility and two-photon vs. one-photon acid production rates (branching ratio). One class of materials,
based on the cycloadduct of a tethered pair of anthracenes, has shown promise under testing at 193nm in acetonitrile.
Sufficient reversibility without acid production, enabled by near-UV exposure, has been achieved. Acid production as a
function of dose shows a clear quadratic component, consistent with a branching ratio greater than 1. The experimental
data also supports a acid contrast value of approximately 0.05 that could in principle be obtained with this molecule
under a pitch division double-exposure scenario.
Novel RET-Pixelated Phase Mask (PPM) is proposed as a novel Resolution Enhancement Technique (RET). PPM is
made of pixels of various phases with lateral dimensions significantly smaller than the illuminating radiation
wavelength. Such PPM with a singular choice of pixel dimensions acts as a mask with variable phase and transmission
due to radiation scattering and attenuation on pixel features with the effective intensity and phase modulated by the
pixel layout. Key properties of the pixelated phase masks, the steps for their practical realization, and the benefits to
random logic products discussed. Wafer patterning performance and comparative functional yield results obtained for a
65nm node microprocessor patterned with PPM, as well as current PPM limitations are also presented.
This work describes the advantages, tolerances and integration issues of using Pixelated Phase Masks for patterning
logic interconnect layers. Pixelated Phase Masks (PPMs) can act as variable high-transmission attenuated phase shift
masks where the pixelated phase configuration simultaneously optimizes OPC and SRAF generation. Thick mask
effects help enable PPMs by allowing larger minimum pixel sizes and phase designs with near equal sized zero and piphase
regions. PPMs with a 3-tone pixel mask (un-etched glass, etched glass, chrome) offer more flexible patterning
capability compared to 2-tone pixel mask (no chrome) style but at the detriment of a more complex mask making
process. We describe the issues and opportunities associated with using PPMs for patterning a 65nm generation first
level metal layer of a micro-processor.
In June 2007, Intel announced a new pixelated mask technology. This technology was created to address the problem
caused by the growing gap between the lithography wavelength and the feature sizes patterned with it. As this gap has
increased, the quality of the image has deteriorated. About a decade ago, Optical Proximity Correction (OPC) was
introduced to bridge this gap, but as this gap continued to increase, one could not rely on the same basic set of
techniques to maintain image quality. The computational lithography group at Intel sought to alleviate this problem by
experimenting with additional degrees of freedom within the mask. This paper describes the resulting pixelated mask
technology, and some of the computational methods used to create it. The first key element of this technology is a thick
mask model. We realized very early in the development that, unlike traditional OPC methods, the pixelated mask would
require a very accurate thick mask model. Whereas in the traditional methods, one can use the relatively coarse
approximations such as the boundary layer method, use of such techniques resulted not just in incorrect sizing of parts of
the pattern, but in whole features missing. We built on top of previously published domain decomposition methods, and
incorporated limitations of the mask manufacturing process, to create an accurate thick mask model. Several additional
computational techniques were invoked to substantially increase the speed of this method to a point that it was feasible
for full chip tapeout. A second key element of the computational scheme was the comprehension of mask
manufacturability, including the vital issue of the number of colors in the mask. While it is obvious that use of three or
more colors will give the best image, one has to be practical about projecting mask manufacturing capabilities for such a
complex mask. To circumvent this serious issue, we eventually settled on a two color mask - comprising plain glass and
etched glass. In addition, there were several smaller manufacturability concerns, for example a "1X1" glass pillar (an
isolated 0 phase pixel) were susceptible to collapse under the stress of mask processing, and therefore these had to be
constrained out of the final configuration. A third key element was defining the objective function. We experimented
with a large number of choices and eventually settled on a form that allows us to trade-off fidelity and contrast. A fourth
key element was the optimization algorithm. The number of possible configurations for a trillion pixels present on our
final product mask is greater than the number of total elementary particles in the known universe, so finding the
proverbial needle in this haystack was difficult to say the least. We chose a mixture of stochastic and direct descent
algorithms to find an arrangement that meets the demands. While we have not proved we are close to the absolute global
minimum, we conducted several experiments to suggest this is the case. A fifth key element, and a large one at that, was
scaling up our software system from micron length scale to centimeter length scale required for full chip tapeout. This
software, in turn, has several key components - hierarchy handling, the non-trivial handling of pixelated domain
boundaries, repair of regions not converged in terms of image quality, and verification of the entire assembled database.
All elements described above were validated through the tapeout of an actual mask to pattern the most complex metal
layer for the leading 65nm node microprocessor in high volume manufacturing. This very first experimental tapeout
resulted in wafer parts yield comparable to yields on mass produced wafers made with production 65nm technology.
Pixelated phase masks rendered from computational lithography techniques demand one generation-ahead mask
technology development. In this paper, we reveal the accomplishment of fabricating Cr-less, full field, defect-free
pixilated phase masks, including integration of tapeout, front-end patterning and backend defect inspection, repair,
disposition and clean. This work was part of a comprehensive program within Intel which demonstrated microprocessor
To pattern mask pixels with lateral sizes <100nm and vertical depth of 170nm, tapeout data management, ebeam write
time management, aggressive pattern resolution scaling, etch improvement, new tool insertion and process integration
were co-optimized to ensure good linearity of lateral, vertical dimensions and sidewall angle of glass pixels of arbitrary
pixelated layout, including singlets, doublets, triplets, touch-corners and larger scale features of structural tones
including pit/trench and pillar/mesa. The final residual systematic mask patterning imperfections were corrected and
integrated upstream in the optical model and design layout.
The volume of 100nm phase pixels on a full field reticle is on the order tera-scale magnitude. Multiple breakthroughs in
backend mask technology were required to achieve a defect free full field mask. Specifically, integration of aerial
image-based defect inspection, 3D optical model-based high resolution ebeam repair and disposition were introduced.
Significant reduction of pixel mask specific defect modes, such as electro static discharge and glass pattern collapse,
were executed to drive defect level down to single digit before attempt of repair. The defect printability and repair yield
were verified downstream through silicon wafer print test to validate defect free mask performance.
Multiple paths exists to provide lithography solutions pursuant to Moore's Law for next 3-5 generations of
technology, yet each of those paths inevitably leads to solutions eventually requiring patterning at k1 < 0.30
and below. In this article, we explore double exposure single development lithography for k1 ≥ 0.25 (using
conventional resist) and k1 < 0.25 (using new out-of-sight out-of-mind materials). For the case of k1 ≥ 0.25, we
propose a novel double exposure inverse lithography technique (ILT) to split the pattern. Our algorithm is based
on our earlier proposed single exposure ILT framework, and works by decomposing the aerial image (instead of
the target pattern) into two parts. It also resolves the phase conflicts automatically as part of the decomposition,
and the combined aerial image obtained using the estimated masks has a superior contrast.
For the case of k1 < 0.25, we focus on analyzing the use of various dual patterning techniques enabled by the
use of hypothetic materials with properties that allow for the violation of the linear superposition of intensities
from the two exposures. We investigate the possible use of two materials: contrast enhancement layer (CEL) and
two-photon absorption resists. We propose a mathematical model for CEL, define its characteristic properties,
and derive fundamental bounds on the improvement in image log-slope. Simulation results demonstrate that
double exposure single development lithography using CEL enables printing 80nm gratings using dry lithography.
We also combine ILT, CEL, and DEL to synthesize 2-D patterns with k1 = 0.185. Finally, we discuss the viability
of two-photon absorption resists for double exposure lithography.
Area density scaling in integrated circuits, defined as transistor count per unit area, has followed the famous
observation-cum-prediction by Gordon Moore for many generations. Known as "Moore's Law" which predicts density
doubling every 18-24 month, it has provided all important synchronizing guidance and reference for tools and materials
suppliers, IC manufacturers and their customers as to what minimal requirements their products and services need to
meet to satisfy technical and financial expectations in support of the infrastructure required for the development and
manufacturing of corresponding technology generation nodes. Multiple lithography solutions are usually under
considerations for any given node. In general, three broad classes of solutions are considered: evolutionary - technology
that is extension of existing technology infrastructure at similar or slightly higher cost and risk to schedule;
revolutionary - technology that discards significant parts of the existing infrastructure at similar cost, higher risk to
schedule but promises higher capability as compared to the evolutionary approach; and last but not least, disruptive -
approach that as a rule promises similar or better capabilities, much lower cost and wholly unpredictable risk to
schedule and products yields. This paper examines various lithography approaches, their respective merits against
criteria of respective infrastructure availability, affordability and risk to IC manufacturer's schedules and strategy
involved in developing and selecting best solution in an attempt to sort out key factors that will impact the decision on the lithography choice for large-scale manufacturing for the future technology nodes.
The resolution limits of optical lithography are usually described by the well-known Raleigh criterion, CD = κ1 (λ/NA). One of the biggest challenges in optical lithography is to reliably print contact holes patterns with κ1 ~ 0.35 using a hyper NA system (NA > 1) especially for relatively small (m × n) arrays. Polarization effects cause deviations from a simple (λ/NA) scaling large NA values. For an isolated hole, n = 1 and for large arrays, n ⪆ 15, the spectral content is mainly contained in the lowest diffracted orders that are captured within the NA of the imaging lens. The most difficult situation is for small arrays (m, n ≈ 2, 3, 4) where the spectral features are broader more of the important image information is contained in the higher diffraction orders. The patterning of contact holes also suffers from tight dose tolerances and high mask error enhancement factors (MEEF) as both the feature and array sizes decrease. A detailed PROLITHTM vector simulation study is reported for three different approaches to printing, isolated contact holes and small to large contact hole arrays with a κ1 of 0.35 and NAs of 1.05 and 1.3: 1) imaging interferometric lithography (IIL, with a single mask and multiple exposures incorporating pupil plane filters), 2) two-exposure dipole illumination, and 3) alternating phase shift masks (alt-PSM). Only the IIL scheme is capable of printing smaller (m, n ≤ 10) at this low κ1 factor. Single exposure alt-PSM does not allow for the necessary polarization control. Periodic assist features provide improved resolution, depth of focus and MEEF, at the expense of a more complex mask and additional nonprinting area surrounding the contact holes.
Intel will start high volume manufacturing (HVM) of the 65nm node in 2005. Microprocessor density and performance trends will continue to follow Moore's law and cost-effective patterning solutions capable of supporting it have to be found, demonstrated and developed during 2002-2004. Given the uncertainty regarding the readiness and respective capabilities of 157nm and 193nm lithography to support 65nm technology requirements, Intel is developing both lithographic options and corresponding infrastructure with the intent to use both options in manufacturing. Development and use of dual lithographic options for a given technology node in manufacturing is not a new paradigm for Intel: whenever introduction of a new exposure wavelength presented excessive risk to the manufacturing schedule, Intel developed parallel patterning approaches in time for the manufacturing ramp. Both I-line and 248nm patterning solutions were developed and successfully used in manufacturing of the 350nm node at Intel. Similarly, 248nm and 193nm patterning solutions were fully developed for 130nm node high volume manufacturing.
157-nm has emerged as the most favorable post 193-nm lithography choice. Significant progress has been made since it was initiated at MIT-LL in 1997. Material is perhaps the most critical issue of 157nm lithography in all areas of concern: optics, resist, and mask. CaF2 is the only material currently shown to be feasible for 157-nm lens though other materials namely BaF2 are being developed as secondary material. Due to limited availability of materials in conjunction with the difficulty in developing line-narrowed F2 laser, optics design is limited. Catadioptric lens design is being considered by most major exposure tool suppliers. Meanwhile, most conventional organic materials are opaque at 157-nm. New fluorinated polymers have been discovered and currently being developed for both resist and pellicle applications. Good progress in this area has been reported at the Sematech’s First 157-nm Symposium at Dana Point, California, May 9-11, 2000. Alternative approaches are also being developed. One example is thin layer resist process using conventional chemistry to overcome high absorption issue at 157-nm. Another is the so-called hard pellicle, i.e., a ~300-um thick film of the newly developed dry-fluorine doped fused silica is used instead of the typical 1-um thin organic membrane. On the other hand, major accomplishment has been reached in the field of mask blank material to replace the existing one for 157-nm application. The new dry and fluorine-doped fused silica has been shown to have good transmittance and radiation durability. Blank and reticle making using this newly developed material have been reported to be satisfactory even with current processes. High absorption at 157-nm also leads to other requirements such as surface molecular contamination removal and system purging. Therefore, reticle handling has become critical in that reticle purging, In-Situ cleaning and ESD prevention must be considered. While recognized to be issues, possible technical solutions have been proposed. This paper will provide an overview of 157-nm lithography development. Results will be presented to show progress. Critical issues covering exposure tool, resist and mask will be discussed.
The application of overlay modeling to the description of the observed and predicted overlay errors allows for the multipurpose use of the successful modeling technique in identifying and resolving overlay problems. The presented paper describes the application of overlay modeling in estimating the exposure tool alignment system sensitivity to process/tool interaction and its potential impact on overlay performance. The described methodology is applicable to the characterization of various alignment systems and its use is described in detail. Another use of the overlay model allowed us to uncover large field mismatch and translational errors due to process induced change in wafer size. This discovery prompted the development of new exposure tool capabilities to provide adequate compensation for these overlay components. It is shown that analysis of unmodeled (residual) components of overlay also provided valuable insights into the peculiarities of exposure tool and process/overlay interaction.
A study of linewidth variations across commercial stepper exposure fields suggests that variations in local value of partial coherence across the exposure field might be responsible for the excessive character of linewidth variance. A methodology to estimate the local value of partial coherence (LVPC) at a random point in the stepper exposure field is proposed and discussed. Estimation of the local value of the partial coherence summarized across the tested exposure field is represented as a 'Coherence map' of the stepper field. For a stepper under test, such a map revealed significant deviation in the local values of the partial coherence from the designed value. Estimated LVPC variation fully accounted for 'excessive' across field linewidth variation as well as for its orientational dependency. Several means of improving line width control in the presence of variance in LVPC are suggested. The impact of the presence of localized partial coherence in the exposure systems used with PSM and OPC technologies is analyzed briefly. Sensitivity to LVPC variations with the suggested monitor design and ways to improve t are also discussed.