The importance of in-die sampling using E-beam solution on yield improvement Yu Zhanga, Biqiu Liua, Cong Zhanga, Yuyang Biana, Song Gaoa, Yifei Zhua, Xiaobo Guoa, Jun Huanga, Yaniv Abramovitzb , Qiang Zhoub, Uri Smolyanb, Omri Baumb, Amit Zakayb, Rohit Kumar Singhb (a) Shanghai Huali Integrated Circuit Manufacturing Corporation, Pudong New District, Shanghai, China; (b) PDC business group, Applied Materials, Rehovot, Israel As technology progress with scaling to meet the market requirements, the patterning characterization of dense features suffers a significant challenge for current optic tools, and measurement accuracy will be an important index and great challenge as well. Patterning can mostly be characterized with index of overlay measurement. When you break down the budget of the overlay error, one of the challenges is a gap between measurement results in scribe and device, which provide improper information to be used in correction or process anomaly (excursion) detection, resulting in a low yield at the end of the production process. An eBeam tool, using high electron landing energies while utilizing the Elluminator technology for improvement backscattered electrons (BSE) imaging efficiency, can be utilized to directly capture OVL performance of device unit in die, including local and global level, due to BSE function of eBeam tool. In this paper, we demonstrate overlay measurement of M0 to Poly line in device for advanced logic node, obtaining measurement gap between Overlay in-die and scribe line to capture the actual behavior of device unit in die. Massive overlay data measured by optical and eBeam tool with have been analyzed in detail. Keywords: Overlay, eBeam, yield, CDSEM, accuracy, in-die,
The advanced logic node is continuously shrinking toward 1nm and EUV lithography is one of the main technical drivers to reach better patterning resolution combined with reduced process steps. Along with this design rule shrink, the patterning control with the metric of Edge Placement Error (EPE), of which main contributors are CD and overlay error, becomes more and more critical. EPE-aware process margin studies1 are of growing interest and focus on advanced nodes. However, the studies are mostly focused on single type of device feature or hot spot (HS) and the EPE budget breakdown is analyzed through the data set from different process steps, metrology tools (SEM, OM), and measurement targets (device structure, scribe line target) which inherently contains the problem of data integrity and proximity2. Due to the complicated and localized process loading of the various pattern on logic device the EPE analysis is required on diverse critical device features (HS’s) which shows different fingerprint of EPE due to the process loadings and multi-patterning effects among unit process characteristics. To accomplish this multiple HS EPE-aware analysis, the measurement must be taken at various real device pattern. This requirement leads to data collection with an e-beam tool, using high electron landing energies while utilizing the ElluminatorTM technology for improvement backscattered electrons (BSE) imaging efficiency. This is the unique and right approach to directly capture CD and overlay simultaneously in die, on device, multiple HS’s in local and global level. In this paper, we will demonstrate the EPE budget analysis on various on device HS which results in the different process fingerprint due to the local process loading effect. The all-in-one and on device pattern measurement is the essential prerequisite capability on this study. The data is captured from the high-quality e-beam image which delivers a CD-SEM comparable precision, low TMU overlay metrology on real device. We demonstrate that with the multi HS EPE-aware analysis from the all-in-one on device data, the balanced EPE margin is achieved through the co-optimized correctable with the weighted factors among HS’s to increase yield at end of line. Keywords: CD, Overlay, e-beam, EPE, accuracy, on device, HS, yield
Optical overlay metrology has been used for years as the baseline for overlay control, measuring an optical target in the scribe line with optimized design to best match the on-product overlay. However, matching the optical target overlay measurements to the real on-product overlay becomes a serious challenge for most advanced technology nodes and forces the industry to develop different or complementary solutions. To identify and better quantify the different, well-known overlay accuracy detractors, in this work we have used optical and state-of-the-art electron beam technologies (eBeam) to measure on-product and on-optical target overlay errors of a wafer processed at imec using 5 nm technology node design rules and intentionally introduced overlay skews of +10 and -10 nm in x and y axis. The overlay errors as measured by the SEM eBeam system, equipped with elluminator™ technology which enables fast see through measurements of overlay which has been compared with (X-sectional) STEM-HAADF reference overlay metrology data. The on-product and optical target SEM overlay measurements show very similar wafer maps, in line with the applied overlay errors during the lithography exposure step. eBeam and TEM data show excellent correlation for the on-product overlay errors and the eBeam data also reveal a significant bias of ~ 6 nm between on-product and on-target overlay errors. From these results it can be concluded that manufacturing of advanced devices which require accurate OPO control, will need new metrology strategies that combine eBeam and optical or, eventually, use only eBeam technologies to guarantee effective overlay control with sufficient accuracy.
Node to node design rule are shrinking to enable better performance envelope in storage, computing power and electrical usage. A major part of every technology development is verification of the actual device overlay for thick stacks. Today the IC manufactures utilize TEM, Fib and other methods to understand the impact of overlay for thick stacks. These methods, which are considered as a “ground truth” of the fab, can give very good resolution of the features shape characteristics, material contrast, metrology and defectivity. That said, some are destructive and have long time to results. Another approach for thick stack is to use eBeam high kV landing with elluminator technology, this enables fast see through measurements of overlay, yet this approach has also limitation where layer stack thickness exceeds see through imaging capability while chipmakers still require seeing the bottom layer to measure the overlay.
In this paper, we propose a flow of accurate in-line runtime delayer method flowed by an eBeam elluminator technology for overlay verification as an extension of current eBeam measurement capabilities. This flow can be complimentary for different applications space where there’s imaging limitation of the eBeam. The excellent local delayer control enables shorter time to root cause, process and design verification metrology (as a “golden ruler”) in runtime fab.
The work is based on IMEC frontend wafer at source drain Implant process steps after Hard Mask Etch. Looking at device features we explore the accuracy of new flow in sampling fins, dummy gate and Hard mask openings for implant process steps. Reference eBeam metrology will verify the accuracy of the delayer metrology.
We present a novel metrology target design framework using the scanner exit pupil wavefront analysis together with Zernike sensitivity analysis (ZSA) based on the Monte-Carlo technique. The proposed method enables the design of robust metrology targets that maximize target process window (PW) while minimizing placement error discrepancies with device features in the presence of spatial and temporal variation of the aberration characteristics of an exposure tool. Knowing the limitations of lithography systems, design constraints, and detailed lithography information including illumination, mask type, etc., we can successfully design an optimal metrology target. We have validated our new metrology target design (MTD) method for one of the challenging DRAM active layer consisting of diagonal line and space patterns illuminated by a rotated extreme dipole source. We find that an optimal MTD target gives the maximized PW and the strong device correlation, resulting in the dramatic improvement of overall overlay performance. The proposed target design framework is completely general and can be used to optimize targets for different lithography conditions. The results from our analysis are both physically sensible and in good agreement with experimental results.