Node to node design rule are shrinking to enable better performance envelope in storage, computing power and electrical usage. A major part of every technology development is verification of the actual device overlay for thick stacks. Today the IC manufactures utilize TEM, Fib and other methods to understand the impact of overlay for thick stacks. These methods, which are considered as a “ground truth” of the fab, can give very good resolution of the features shape characteristics, material contrast, metrology and defectivity. That said, some are destructive and have long time to results. Another approach for thick stack is to use eBeam high kV landing with elluminator technology, this enables fast see through measurements of overlay, yet this approach has also limitation where layer stack thickness exceeds see through imaging capability while chipmakers still require seeing the bottom layer to measure the overlay.
In this paper, we propose a flow of accurate in-line runtime delayer method flowed by an eBeam elluminator technology for overlay verification as an extension of current eBeam measurement capabilities. This flow can be complimentary for different applications space where there’s imaging limitation of the eBeam. The excellent local delayer control enables shorter time to root cause, process and design verification metrology (as a “golden ruler”) in runtime fab.
The work is based on IMEC frontend wafer at source drain Implant process steps after Hard Mask Etch. Looking at device features we explore the accuracy of new flow in sampling fins, dummy gate and Hard mask openings for implant process steps. Reference eBeam metrology will verify the accuracy of the delayer metrology.
Optical overlay metrology has been used for years as the baseline for overlay control, measuring an optical target in the scribe line with optimized design to best match the on-product overlay. However, matching the optical target overlay measurements to the real on-product overlay becomes a serious challenge for most advanced technology nodes and forces the industry to develop different or complementary solutions.
The overlay inaccuracy is usually made of 3 components: target to device different design, target location vs. in-die and optical ambiguity. In this work, we have separated the elements by measuring: overlay errors optically on the optical targets in scribe and in-die, measuring with high electron collection efficiency beam (e-beam) elluminator technology on-device and on-optical targets located in the scribe and in-die. The on-device and optical targets as measured by (top-down) e-beam and optical have been compared with (X-sectional) STEM-HAADF for reference overlay metrology data.
The analysis was done on a wafer processed at imec using 5 nm technology node design rules and intentionally introduced overlay skews of +10 and -10 nm in x and y axis.
The on-product and optical target SEM overlay measurements show very similar wafer maps, in line with the applied overlay errors during the lithography exposure step. E-beam and TEM data show excellent correlation for the on-product overlay errors and the e-beam data also reveal a significant bias of ~ 6 nm between on-product and on-target overlay errors. The correlation of e-beam and optical overlay data from the optical targets show an even larger overlay error bias if these targets are measured with optical overlay equipment.
This can indicate that advanced devices, which requires accurate OPO control, will need new metrology strategies that combine e-beam and optical or only e-beam to reach sufficient accuracy.
We present a novel metrology target design framework using the scanner exit pupil wavefront analysis together with Zernike sensitivity analysis (ZSA) based on the Monte-Carlo technique. The proposed method enables the design of robust metrology targets that maximize target process window (PW) while minimizing placement error discrepancies with device features in the presence of spatial and temporal variation of the aberration characteristics of an exposure tool. Knowing the limitations of lithography systems, design constraints, and detailed lithography information including illumination, mask type, etc., we can successfully design an optimal metrology target. We have validated our new metrology target design (MTD) method for one of the challenging DRAM active layer consisting of diagonal line and space patterns illuminated by a rotated extreme dipole source. We find that an optimal MTD target gives the maximized PW and the strong device correlation, resulting in the dramatic improvement of overall overlay performance. The proposed target design framework is completely general and can be used to optimize targets for different lithography conditions. The results from our analysis are both physically sensible and in good agreement with experimental results.