An integrated 18 GHz double-balanced direct down-conversion mixer and emitter degenerated quadrature VCO is designed and fabricated in IBM 47 GHz ft SiGe BiCMOS process. A novel headroom optimization scheme is proposed to optimize mixer conversion gain and linearity. The mixer uses an LC tank to reduce voltage supply. With a 3.3 V supply voltage the mixer core consumes 16.5mW and the output buffer matched to 50 Ω consumes 33mW. Measurements indicate a conversion gain of 4.5 dB, a double-side band noise figure of 7.1dB, an IIP3 of -1dBm, and 1dB compression point at -12.2dBm output power. The mixer has the best figure-of-merit compared to recently published mixers operating at similar frequencies in a Si-based process. The voltage controlled oscillator uses an emitter degenerated LC oscillator core with both SiGe HBT and CMOS buffers to achieve oscillation providing direct downconversion for the aforementioned mixer. The oscillator has two anti-phase coupled cores to lower the phase noise through frequency locking, the unused output ports terminated with 50 Ω. The two circuits (several variants of each) are integrated monolithically, with an oscillator breakout with a phase noise performance of -99 dBc/Hz (at 1 MHz separation) with 1 GHz tuning range while pulling 19 mA from a 2.5 V rail. The paper will include all the necessary design equations used to optimize both circuits along with comparisons with other published results.