As the technology node for the semiconductor manufacturing approaches advanced nodes, the scattering-bars (SBs) are more crucial than ever to ensure a good on-wafer printability of the line space pattern and hole pattern. The main pattern with small pitches requires a very narrow PV (process variation) band. A delicate SB addition scheme is thus needed to maintain a sufficient PW (process window) for the semi-iso- and iso-patterns. In general, the wider, longer, and closer to main feature SBs will be more effective in enhancing the printability; on the other hand, they are also more likely to be printed on the wafer; resulting in undesired defects transferable to subsequent processes. In this work, we have developed a model based approach for the scattering-bar printing avoidance (SPA). A specially designed optical model was tuned based on a broad range of test patterns which contain a variation of CDs and SB placements showing printing and non-printing scattering bars. A printing threshold is then obtained to check the extra-printings of SBs. The accuracy of this threshold is verified by pre-designed test patterns. The printing threshold associated with our novel SPA model allows us to set up a proper SB rule.
The optical proximity correction (OPC) systematically adds the bias with respect to the designs to the mask, correcting the proximity effects associated with sub-wavelength features. Due to the complex nature of main features of the circuits, even a carefully tuned OPC recipe can yield thousands of weak points for each tape-out. Some of these weak points require manual fixings which might demand considerable amount of effects from engineers. It has been found that for different tape-outs, the resulting OPC patterns that require manual fixings share quite a lot commonalities or are even the same. Repeatedly performing manual fixings for the same type of weak points for different tape-outs presents a waste of human efforts. We therefore constructed a pattern matching library for these types of weak points. At the very of beginning of an OPC recipe, the design patterns of these types of weak points are used to scan the whole chip and find the same patterns. Then, the pre-calculated OPC and SB (scattering bar) layers are pasted to the relevant positions. The pasted patterns will be kept fixed and serve as boundary condition for the subsequent model-based OPC. The final resulting OPC layer will be free of those types of weak points that require manual fixings.
The optical proximity correction (OPC) designs a biased mask so as to ensure the after-development-inspection (ADI) contours could be on target. Meanwhile, the lithographic manufacture process is approaching the sub 28 nm technology node, imposing a tremendous challenge on OPC engineers. Even a well-tuned OPC recipe can render many off-target simulated contours for the most up-to-date chip designs; and these off-target contours indicate highly possible on wafer weak points. We have recently developed a high-performance repair flow that can automatically correct these OPC weak points based on the retargeting procedure. It is expected that one has to take both nominal and process window (PW) conditions into account to avoid potential on wafer weak points. For the contact holes, we require the nominal CD and PW CD be at least <i>CD</i><sub>nom</sub> and <i>CD</i><sub>pw</sub>, respectively. In some cases, it could be difficult to satisfy both nominal and PW CD constraints which may pose conflicts to each other. In this work, various strategies have been used to accommodate such conflicts; for instance, one can release the nominal constraint or replace the PW CD constrain by the PW area constrain. We perform a systematic study on the various specifications of these constraints, in order to select the most optimal setup for the nominal and PW constraints. These optimized specifications may allow us to perform a highly efficient repair on a contact layer.
Traditionally, the optical proximity correction (OPC) is to deliver the solution to ensure the nominal after-development-inspection (ADI) contours on target. As the technology node keeps shrinking to 28nm and beyond, the OPC is expected to cover the lithography process window (PW), etch PW, and overlay margin as well. As a result, more and more advanced functions are included in OPC to achieve the awareness of multiple cost functions, such as the nominal EPE, PW effective EPE, the enclosure of above and underneath layers, and so on. These inclusions are at the cost of the run time and complexity of OPC solution. In this paper, we demonstrated a methodology by adopting design rule check (DRC) algorithm in repair flow to fix hot spots. In accordance to OPC verification check, the subsequent DRC movements were applied to those hot spots only. With a straightforward recipe tuning, a fast convergence of OPC can be achieved. The results exhibit the run time improvement without compromising the OPC performance. We further evaluated by real cases the effects of the DRC-based repair algorithm on the error convergence and final repair effects, by comparing to the standard OPC solution.