As the VLSI technology scales into deep submicron nodes, Double Patterning Technology (DPT) has shown its necessity
for the under 45nm processes. However, the litho-related and process-related issues, such as the overlay control for CD
uniformity, decomposition, feature stitching technology and some other problems make up the main challenges for the
implementation of DPT. Due to Optical Proximity Correction (OPC), the complexity and data volume of DPT increase
dramatically, which severely increase the application cost and create manufacturability problems.
In this paper, we mainly talk about the interactions between DPT and OPC and propose a new Model-Based OPC
methods for the decomposition in DPT procedures. To address the printing problems with cutting sites for feature split,
we introduce an overlap correction method on the stitching locations. For any re-cut and/or redesigned pattern after
verification, we categorize DP decompositions and introduce a new Adaptable OPC (Ad-OPC) algorithm by reusing post
OPC layout to speed up the correction and improve its convergence according to environment surrounding. The method
can be easily incorporated into existing MB-OPC framework. To test this method, total Edge Placement Error (EPE) and
runtime are calculated in our experiments. Results show that over 90% runtime can be saved compared with
conventional OPC procedure. It increases the robustness and friendliness of pattern correction as well as stitches features
As the most important RET (Resolution Enhancement Technology), OPC (Optical Proximity Correction) technology has
been widely used in today's IC manufacturing and is still developing very fast both in its principle and its practice. In
this invited paper, key techniques of OPC are classified and overviewed; progresses of OPC technology in recent years
published in major SPIE symposiums are reviewed as well. Recent research results produced by Zhejiang University's
team are described and reviewed with highlighting. An OPC tool suite named ZOPC, which has been designed to enable
new OPC techniques to be integrated into one platform, is presented. The framework of ZOPC as well as its working
scheme is demonstrated with real examples.
To reduce design spin time, OPC-unfriendly spots in IC layout should be found out by designer before tapeout.
This can be done by firstly running a "trial OPC" step on the layout, followed by running an ORC step
to verify the result. In this paper we introduce a specialized cell-wise OPC method using an edge bias modeling
method to improve the accuracy while keeping the advantage on correction speed, which is dozens of times faster
than traditional model-based OPC method. This makes the algorithm a good choice for "trial OPC".
The correction accuracy of a model-based OPC (MB-OPC) depends critically on its edge offset calculation
scheme. In a normal MB-OPC algorithm, only the impact of the current edge is considered in calculating each
edge offset. As the k1 process factor decreases and design complexity increases, however, the interaction between
the edge segments becomes much larger. As a result, the normal MB-OPC algorithm may not always converge
or converge slowly. Controlling the EPE is thus become harder. To address this issue, a new kind of MB-OPC
algorithm based on MEEF matrix was introduced which is also called matrix OPC. In this paper, a variant of
such matrix OPC algorithm is proposed which is suitable for kernel-based lithography models. Comparing with
that based on MEEF matrix, this algorithm requires less computation in matrix construction. Sparsity control
scheme and RT reuse scheme are also used to make the correction speed be close to a normal one while keeping
its advantages on EPE control.