The resist effect may have a significant impact on source mask optimization (SMO), because the CD change in response to dose, defocus and mask size variations can be substantially modified by the resist effect. In this paper, we elaborate on how the resist effect, represented by compact resist models, changes the cost function of SMO and affects the optimized source shapes and the corresponding lithographic performance. Based on the results, we present the guidelines of using compact resist models in SMO, especially for the case of the negative tone development (NTD) process.
As nodes become smaller and smaller, the OPC applied to enable these nodes becomes more and more sophisticated. This trend peaks today in curve-linear OPC approaches that are currently starting to appear on the roadmap. With this sophistication of OPC, the mask pattern complexity increases. CD-SEM based mask qualification strategies as they are used today are starting to struggle to provide a precise forecast of the printing behavior of a mask on wafer. An aerial image CD measurement performed on ZEISS Wafer-Level CD system (WLCD) is a complementary approach to mask CD-SEMs to judge the lithographical performance of the mask and its critical production features. The advantage of the aerial image is that it includes all optical effects of the mask such as OPC, SRAF, 3D mask effects, once the image is taken under scanner equivalent illumination conditions. Additionally, it reduces the feature complexity and analyzes the printing relevant CD.
The appropriate representation of the photomask in the simulation of wafer lithography processes has been shown to be of vital importance for 14-nm and below . This task is difficult, since accurate optical metrology and physical metrology of the three-dimensional mask structure is not always available. OPC models for wafer patterning comprise representations of the mask, the optics, and the photoresist process. The traditional calibration of these models has involved empirical tuning of model parameters to CD-SEM data from printed photoresist patterns. Such a flow necessarily convolves the resist effects and it has been difficult to reliably obtain mask and optical parameters which are most representative of physical reality due to aliasing effects. In this work, we have undertaken to decouple the mask model from the photoresist process by use of the ZEISS Wafer-Level CD (WLCD) tool based upon aerial image metrology. By measuring the OPC test pattern mask with WLCD, the mask parameters in the OPC model can be tuned directly without interference of resist effects. This work utilized 14-nm,10-nm, and 7-nm node masks, and we demonstrate that the use of such a flow leads to the most predictive overall OPC models, and that the mask parameters resulting from this flow more closely match the expected physical values. More specifically, the mask corner rounding, sidewall angle, and bias values were tuned to the WLCD data instead of the wafer CD SEM data, and resulted in improved predictive capability of the model. Furthermore, other mask variables not traditionally tuned can be verified or tuned by matching simulation to aerial image metrology.
Source Mask Optimization (SMO) has played an important role in technology setup and ground rule definition since the 2x nm technology node. While improvements in SMO algorithms have produced higher quality and more consistent results, the accuracy of the overall solution is critically linked to how faithfully the entire patterning system is modeled, from mask down to substrate. Fortunately, modeling technology has continued to advance to provide greater accuracy in modeling 3D mask effects, 3D resist behavior, and resist phenomena. Specifically, the Domain Decomposition Method (DDM) approximates the 3D mask response as a superposition of edge-responses.<sup>1</sup> The DDM can be applied to a sectorized illumination source based on Hybrid-Hopkins Abbe approximation,<sup>2</sup> which provides an accurate and fast solution for the modeling of 3D mask effects and has been widely used in OPC modeling. The implementation of DDM in the SMO flow, however, is more challenging because the shape and intensity of the source, unlike the case in OPC modeling, is evolving along the optimization path. As a result, it gets more complicated. It is accepted that inadequate pupil sectorization results in reduced accuracy in any application, however in SMO the required uniformity and density of pupil sampling is higher than typical OPC and modeling cases. In this paper, we describe a novel method to implement DDM in the SMO flow. The source sectorization is defined by following the universal pixel sizes used in SMO. Fast algorithms are developed to enable computation of edge signals from each fine pixel of the source. In this case, each pixel has accurate information to describe its contribution to imaging and the overall objective function. A more continuous angular spectrum from 3D mask scattering is thus captured, leading to accurate modeling of 3D mask effects throughout source optimization. This method is applied on a 2x nm middle-of-line layer test case. The impact of the 3D mask model accuracy on the source profile and corresponding lithographic performance is studied in detail. Furthermore, the impact of using a compact resist model in SMO is also investigated by using the same test case.
In this paper, we present the approach and results of layer-aware source mask target optimization. In this approach, the design target is co-optimized during source mask optimization (SMO) by considering inter-layer constraints. We tested the method on a 2x nm node metal layer by using both standard and customized cost functions for source optimization. Variable targets were defined for two process window limiting critical pattern cells, with contact-to-metal and metal-tovia coverage rules taken into consideration. The results indicate that layer-aware source mask target optimization gives consistent process window improvement over conventional SMO. The optimized targets prove to be a good balance between lithography process window and post-etch inter-layer coverage margin.
With the introduction of negative tone develop (NTD) resists to production lithography nodes, multiple NTD resist modeling challenges have surpassed the accuracy limits of the existing modeling infrastructure developed for the positive polarity process. We report the evaluation of two NTD resist modeling algorithms. The new modeling terms represent, from the first principles, the NTD resist mechanisms of horizontal shrink and horizontal development bias. Horizontal shrink describes the impact of the physical process of out-gassing on remaining resist edge location. Horizontal development bias accounts for the differential in the peak and minimum development rate with exposure intensity observed in NTD formulations. We review specific patterning characteristics by feature type, modeling accuracy impact presented by these NTD mechanisms, and their description in our compact models (Compact Model 1, CM1). All the new terms complement the accuracy advantage observed with existing CM1 resist modeling infrastructure. The new terms were tested on various NTD layers. The results demonstrate consistent model accuracy improvement for both calibration and verification. Furthermore, typical NTD model fitting challenges, such as large SRAF-induced wafer CD jump, can be overcome by the new NTD terms. Finally, we propose a joint-tuning approach for the calibration of compact models for the NTD resist.
In optical proximity correction (OPC), the sub-resolution assist feature (SRAF) has been used to enhance the process window of main structures. However, the printing of SRAF on wafer is undesirable as this may adversely degrade the overall process yield if it is transferred into the final pattern. A reasonably accurate prediction model is needed during OPC to ensure that the SRAF placement and size have no risk of SRAF printing. Current common practice in OPC is either using the main OPC model or model threshold adjustment (MTA) solution to predict the SRAF printing. This paper studies the feasibility of SRAF printing prediction using logistic regression (LR). Logistic regression is a probabilistic classification model that gives discrete binary outputs after receiving sufficient input variables from SRAF printing conditions. In the application of SRAF printing prediction, the binary outputs can be treated as 1 for SRAFPrinting and 0 for No-SRAF-Printing. The experimental work was performed using a 20nm line/space process layer. The results demonstrate that the accuracy of SRAF printing prediction using LR approach outperforms MTA solution. Overall error rate of as low as calibration 2% and verification 5% was achieved by LR approach compared to calibration 6% and verification 15% for MTA solution. In addition, the performance of LR approach was found to be relatively independent and consistent across different resist image planes compared to MTA solution.
At the 20nm technology node, it is challenging for simple resolution enhancements techniques (RET) to achieve sufficient process margin due to significant coupling effects for dense features. Advanced computational lithography techniques including Source Mask Optimization (SMO), thick mask modeling (M3D), Model Based Sub Resolution Assist Features (MB-SRAF) and Process Window Solver (PW Solver) methods are now required in the mask correction processes to achieve optimal lithographic goals. An OPC solution must not only converge to a nominal condition with high fidelity, but also provide this fidelity over an acceptable process window condition. The solution must also be sufficiently robust to account for potential scanner or OPC model tuning. In many cases, it is observed that with even a small change in OPC parameters, the mask correction could have a big change, therefore making OPC optimization quite challenging. On top of this, different patterns may have significantly different optimum source maps and different optimum OPC solution paths. Consequently, the need for finding a globally optimal OPC solution becomes important. In this work, we introduce a holistic solution including source and mask optimization (SMO), MB-SRAF, conventional OPC and Co-Optimization OPC, in which each technique plays a unique role in process window enhancement: SMO optimizes the source to find the best source solution for all critical patterns; Co-Optimization provides the optimized location and size of scattering bars and guides the optimized OPC solution; MB-SRAF and MB-OPC then utilizes all information from advanced solvers and performs a globally optimized production solution.
A robust optical proximity correction (OPC) model must include process variation to be effective in volume manufacturing. Often, calibration of an OPC model is based on data from a single scanner. However, scanner and mask three dimension (3D) effects have been found to affect printing performance and OPC model effectiveness . OPC model robustness is improved if the fingerprints of different scanners are matched as closely as possible. Scanner source map or boundary condition variations can cause isolated and dense feature focus differences between different scanners. The scanner used to build a robust OPC model should have a minimum focus difference between isolated and dense features. Mask 3D effects must be included in OPC model building. Even if the design data is the same, mask 3D effects will vary by different advanced blank film stacks and model fitting will lead to different results. In this work, the effects of focus differences between nested and isolated features for OPC model building are quantified. In addition, mask 3D effect contributions to OPC models will also be illustrated. OPC model tolerance to variation is shown using data from multiple scanners and mask topographies and methodologies to optimize OPC models are presented. The data confirms that different absorber thickness, and n and k values, for advanced binary masks will influence the boundary conditions and effect lithographic performance. A thinner absorber demonstrated better CD prediction than thicker blanks in semi-dense and isolated patterns for both CDTP and inverse CDTP. It also shows that the thinner absorber has better inverse linearity in small isolated features, and has much better prediction for large isolated patterns. The generation of OPC models must include variations due to mask material properties and scanner optical variations to provide robust performance in manufacturing.
In this paper, we present the approach and results of resist profile aware source mask optimization (SMO). In this approach, the cost functions for optimization include the image properties calculated not only from the resist bottom image planes, but also from the top image planes. Consequently, the optimized source and mask shapes are a good balance between the process window for the bottom CD’s, and top CD control to ensure a straight resist profile favorable for the etching process. We built up the flow of resist profile aware SMO and implemented it on a 1× nm node back-end layer. Two best candidate sources, SMO1 and SMO2 were generated from the conventional SMO flow and the resist profile aware SMO flow, respectively. The simulation results indicate that a better resist profile is achieved by SMO2, although it gives rise to a relatively smaller overlapping process window evaluated at the resist bottom. Wafer data including bottom CD measurement for critical pattern clips and cross-sectional SEM images from selected patterns have shown good matching with the simulation results, indicating that resist-profile aware SMO is a feasible approach to optimize the illumination sources for a reasonable bottom CD based process window as well as favorable resist profiles.
One of the objectives of a robust optical proximity correction (OPC) model is to simulate the process variation including
3D mask effects or mask models for different mask blanks. Assuming that the data of different reticle blanks is the same,
the wafer data should be a close match for the same OPC model. In order to enhance the robustness of the OPC model,
the 3D mask effects need to be reduced. A test of this would be to ensure a close match of the so called fingerprints of
different reticle blanks at the wafer level. Features for fingerprint test patterns include “critical dimension through pitch”
(CDTP), “inverse CDTP”, and “linearity patterns” and critical dimension (CD) difference of disposition structures. In
this manuscript the proximity matching of implant layers on chrome on glass (COG) and advance binary reticle blanks
will be demonstrated. We will also investigate the influence of reticle blank material including reticle process on isolated
and dense features upon the proximity matching for 28 nm high volumes ArF layers such as implant and 2X metal
layers. The OPC model verification has been done successfully for both bare wafer and full field wafer for implant
layers. There is comparable OPC model for advanced binary and COG reticle. Moreover, the wafer critical dimension
uniformity (CDU) results show that advance binary has much better wafer CDU then COG. In spite of higher reticle cost
when switching over to advanced binary, there is a considerable cost reduction for the wafer fab which includes a 39%
savings in total reticle cost as well as cost reduction due to minimal line holds (LH), wafer reworks and scraps due to
Source Mask Optimization (SMO) has become an integral part of resolution enhancement techniques (RET) for almost all critical layers at advanced technology nodes. Over the past couple of years, various flows have emerged for integrating SMO into mainstream RET selection. These flows revolve mainly around clip selection, resist model, verification and analysis metrics, design rule optimization, and so on. There has also been strong emphasis on the quality of mask that is conjugated for source selection process. All these variations in analysis and rigorous simulations for flow selection are critical but they also create a bottleneck in overall RET development. In this paper, we demonstrate an initial RET development flow for 20 nm technology with emphasis on quantifying benefits coming from source and mask. We also report challenges that are encountered in the foundry environment when moving from RET development to production. In conclusion, we demonstrate a reliable solution that could be integrated early in RET development and easily adapted for a production environment.
For 28 nm technology node and below resist profiles need to be taken in to consideration during optical proximity correction (OPC) and verification. The low k1 results in a shallower depth of focus and thus thinner resists, which combined with the process limits increases the risk of resist degradation. Only considering the resist critical dimensions at a single focal plane (such as at the bottom of the resist stack) will miss the impact of the resist 3D profile, like top loss or bottom footing, which can transfer to etch hard pattern failures. To date, modeling to study resist 3D profiles has been available using rigorous simulators and has been used as a verification method for hot spots captured during full chip OPC verification, but not for full chip verification due to the high computational run time cost. This paper demonstrates a 3D resist compact OPC model concept and implementation in a full chip OPC and verification flow. The results show significant improvement for full chip OPC quality with a good correlation between simulation and real wafer hot spots. Because resist profiles are not directly correlated to etch failure, the relationship between the resist profile and etch failures and how to characterize the threshold to dispose the hot spots for the 3D compact model was also investigated.
Basic image intensity parameters, like maximum and minimum intensity values (Imin and Imax), image logarithm slope (ILS), normalized image logarithm slope (NILS) and mask error enhancement factor (MEEF) , are well known as indexes of photolithography imaging quality. For full chip verification, hotspot detection is typically based on threshold values for line pinching or bridging. For image intensity parameters it is generally harder to quantify an absolute value to define where the process limit will occur, and at which process stage; lithography, etch or post- CMP. However it is easy to conclude that hot spots captured by image intensity parameters are more susceptible to process variation and very likely to impact yield. In addition these image intensity hot spots can be missed by using resist model verification because the resist model normally is calibrated by the wafer data on a single resist plane and is an empirical model which is trying to fit the resist critical dimension by some mathematic algorithm with combining optical calculation. Also at resolution enhancement technology (RET) development stage, full chip imaging quality check is also a method to qualify RET solution, like Optical Proximity Correct (OPC) performance. To add full chip verification using image intensity parameters is also not as costly as adding one more resist model simulation. From a foundry yield improvement and cost saving perspective, it is valuable to quantify the imaging quality to find design hot spots to correctly define the inline process control margin. This paper studies the correlation between image intensity parameters and process weakness or catastrophic hard failures at different process stages. It also demonstrated how OPC solution can improve full chip image intensity parameters. Rigorous 3D resist profile simulation across the full height of the resist stack was also performed to identify a correlation to the image intensity parameter. A methodology of post-OPC full chip verification is proposed for improving OPC quality at RET development stage and for inline process control and yield improvement at production stage.
Due to the continuous shrinking in half pitch and critical dimension (CD) in wafer processing, maintaining a reasonable
process window such as depth of focus (DOF) & exposure latitude (EL) becomes very challenging. With the source
mask optimization (SMO) methodology, the lithography process window can be improved and a smaller mask error
enhancement factor (MEEF) can be achieved.
In this paper, the Tachyon SMO work flow and methodology was evaluated. The optimum source was achieved through
evaluation of the critical designs with Tachyon SMO software and the simulated performance was then verified on
another test case. Criteria such as DOF, EL & MEEF were used to determine the optimum source achieved from the
evaluation. Furthermore, the process variation band (PV-Band) and the number of hot spot (design weak points) were
compared between the POR and the optimum source. The simulation result shows the DOF, MEEF & worst PV-Band
were improved by 13%, 17% & 12%, respectively with the optimum SMO source.
In order to verify the improvement from the optimum SMO at the silicon level, a new OPC model was recalibrated with
wafer CD from the optimized source. The OPC recipe was also optimized and a reticle was retrofitted with the new OPC.
By comparing the process window, hotspots and defects between the original vs. new reticle, the benefit of the optimized
source was verified on silicon.
As mask feature sizes have shrunk well below the exposure wavelength, the thin mask of Kirchhoff approximation
breaks down and 3D mask effects contribute significantly to the through-focus CD behavior of specific features.
While full-chip rigorous 3D mask modeling is not computationally feasible, approximate simulation methods do
enable the 3D mask effects to be represented. The use of such approximations improves model prediction capability.
This paper will look at a 28nm darkfield and brightfield layer datasets that were calibrated with a Kirchhoff model
and with two different 3D-EMF models. Both model calibration accuracy and verification fitness improvements are
realized with the use of 3D models.
With shrinking feature sizes and error budgets in OPC models, effective pattern coverage and accurate measurement
become more and more challenging. The goal of pattern selection is to maximize the efficiency of gauges used in model
calibration. By optimizing sample plan for model calibration, we can reduce the metrology requirement and modeling
turn-around time, without sacrificing the model accuracy and stability. With the Tachyon pattern-selection-tool, we seek
to parameterize the patterns, by assessing dominant characteristics of the surroundings of the point of interest. This
allows us to represent each pattern with one vector in a finite-dimensional space, and the entire patterns pool with a set
of vectors. A reduced but representative set of patterns can then be automatically selected from the original full set
sample data, based on certain coverage criteria. In this paper, we prove that the model built with 56% reduced wafer data
could achieve comparable quality as the model built with full set data.
OPC model stability is important at low k-1. Unstable OPC model leads to catastrophic OPC failures. For parametric OPC models, one of the major contributions to model instability is inadequate test pattern coverage over the parameter space where actual product designs reside. In this paper, we present a systematic approach to maximizing the coverage of existing test patterns. In this approach, the entire space over which all pattern variants reside is first approximated by varying the pattern dimensions in simple patterns. We call the generated parameter spaces reference domains. Next, regions in the parameter space that are sparsely covered are determined by overlaying parameter data points corresponding to existing test patterns over the reference domains. Systematically analyzing the characteristics of the reference domains, the required test patterns to maximize test pattern coverage can be inferred. Test pattern coverage is hence maximized. In this study, a parametric model with three parameters is considered.
As the critical dimension (CD) in integrated circuit (IC) device reduces, the total overlay budget needs to be more stringent. Typically, the allowable overlay error is 1/3 of the CD in the IC device. In this case, robustness of alignment mark is critical, as accurate signal is required by the scanner’s alignment system to precisely align a layer of pattern to the previous layer. Alignment issue is more severe in back-end process partly due to the influenced of Chemical Mechanical Polishing (CMP), which contribute to the asymmetric or total destroy of the alignment marks. In this paper, the performance of different design of alignment marks on 0.10μm echnology wafer has been evaluated using ASML ATHENATM alignment system. For example, segmented marks with smaller dimensions in terms of width and length are used. Narrow marks are preferable due to the space constraint in the scribe lines. The width of NSPM has been shrunk down to 70% of the SPM and the length remains the same. It is a challenge to the alignment system to collect the NSPM signal and provide comparable alignment capability. The evaluations were completed using short loop wafers, which focus on back-end-of-line via and metal layers in a 90nm Cu dual damascene low k process. The results also look into the overlay performance using different alignment strategies. Offline overlay measurements were performed to verify the results.