Proc. SPIE. 7636, Extreme Ultraviolet (EUV) Lithography
KEYWORDS: Signal to noise ratio, Defect detection, Inspection, Scanning electron microscopy, Wafer inspection, Photomasks, Line width roughness, Extreme ultraviolet lithography, Line edge roughness, Semiconducting wafers
EUVL is the strongest candidate for a sub-20nm lithography solution after immersion double-patterning. There are still
critical challenges for EUVL to address to become a mature technology like today's litho workhorse, ArF immersion.
Source power and stability, resist resolution and LWR (Line Width Roughness), mask defect control and infrastructure
are listed as top issues. Source power has shown reasonably good progress during the last two years. Resist resolution
was proven to resolve 32nm HP (Half Pitch) lines and spaces with good process windows even though there are still
concerns with LWR. However, the defectivity level of blank masks is still three orders of magnitude higher than the
requirement as of today.
In this paper, mask defect control using wafer inspection is studied as an alternative solution to mask inspection for
detection of phase defects on the mask. A previous study suggested that EUVL requires better defect inspection
sensitivity than optical lithography because EUVL will print smaller defects. Improving the defect detection capability
involves not only inspection system but also wafer preparation. A few parameters on the wafer, including LWR and
wafer stack material and thickness are investigated, with a goal of enhancing the defect capture rate for after
development inspection (ADI) and after cleaning inspection (ACI). In addition to defect sensitivity an overall defect
control methodology will be suggested, involving mask, mask inspection, wafer print and wafer inspection.
Lithography process control becomes increasingly challenging as the design rules shrink. To tackle the issue of
identifying the process window for lithography, we systematically compared three different approaches for 45 nm
process wafer with two variables: Inspection mode (FEM or PWQ) and Analysis methodology (Manual or Design Based
Binning). We found that PWQ + DBB provided the best results.
Defect inspection is a challenge in the edge of wafer region and several new inspection tools and techniques have come
to the market to fulfill this inspection need. Current inspection methodology excludes inspection of partial die located at
the wafer edge, which has lead to the development of a technique available for patterned wafer inspection tools to inspect
these partially printed die. In this paper we identify and develop a robust methodology for the characterization and
monitoring of defectivity on the partially printed edge die. The methodology includes the development of methods for
inspection optimisation requirements, characterization and isolation of defect sources, optimisation of clustering and
binning and control of partial die defectivity.