For 2x nm node semiconductor devices and beyond, more aggressive resolution enhancement techniques (RETs) such as source-mask co-optimization (SMO), litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP) are utilized for the low k1 factor lithography processes. In the SADP process, the pattern fidelity is extremely critical since a slight photoresist (PR) top-loss or profile roughness may impact the later core trim process, due to its sensitivity to environment. During the subsequent sidewall formation and core removal processes, the core trim profile weakness may worsen and induces serious defects that affect the final electrical performance. To predict PR top-loss, a rigorous lithography simulation can provide a reference to modify mask layouts; but it takes a much longer run time and is not capable of full-field mask data preparation. In this paper, we first brought out an algorithm which utilizes multi-intensity levels from conventional aerial image simulation to assess the physical profile through lithography to core trim etching steps. Subsequently, a novel correction method was utilized to improve the post-etch pattern fidelity without the litho. process window suffering. The results not only matched PR top-loss in rigorous lithography simulation, but also agreed with post-etch wafer data. Furthermore, this methodology can also be incorporated with OPC and post-OPC verification to improve core trim profile and final pattern fidelity at an early stage.
It’s critical to address the yield issues caused by process specific layout patterns with limited process window. RETs such as PWOPC are introduced to guarantee high lithographic margin, but these techniques cost high run-time when applied to full-chips. There’s also lack of integrated solution to easily identify, define comprehensive patterns and apply different controls and/or constraints over these patterns through different stages of OPC/RET process. In this paper, we study a pattern aware OPC flow that applies PWOPC or specific corrections locally to layouts with critical and yield limiting patterns. Although the full chip PWOPC provides an effective way, it causes great amount of run time penalty and does not achieve optimal process window. Overall, PAOPC achieves the better margins over the hotspots, without sacrificing turnaround time. The study demonstrates the benefit of the new flow with fine grained process window controls over different patterns. This flow get good improvement on defect counts when evaluated on 50 nm node logic devices.
As the scaling down of design rule for high density memory device continues, the contact hole size shrinkage becomes one of the major challenges to patterning. Many shrinkage approaches have been introduced after litho. process, such as chemical shrink, PR reflow, RIE shrink, etc. However, CD uniformity control for these shrink processes is critical, and minimum pitch size is still dominated by the resolution limitation of lithography tools. In this paper, we adopt SADP (self-aligned double patterning) process combined with additional non-critical mask step to form 32nm hp elliptical single row dense and isolated contact holes. The CD uniformity is well controlled by SADP process, and chip size reduction is achievable by this high-density single row layout compared with interlace contact hole design. We also compared this new approach with chemical shrink process, and both the CD uniformity and resolution limit are improved. With optimized step-by-step etch process, we have successfully demonstrated the contact hole patterns on full-structure substrate. For the future application toward sub-2x nm node, this approach is also expectable with mature SADP process.
Resist supplier has successfully demonstrated applying negative tone resist into ArF lithography. It is capable of
achieving 50nm dense line and <30nm isolated space pattern by over dose operation in topcoat-free immersion
lithography. Additionally, using ArF dry system with double exposure could also realize 65nm gridded contact hole
patterns. For specific application, negative PR ArF lithography has better benefit of cost and process control capability
than other approaches. In this paper, we have determined process capability of 65nm gridded contact hole by ArF dry
double patterning and compared with LELE process in terms of DOF, EL and CDU and cost. By continuously
optimizing process parameter, >0.21um DOF and 4.6nm global CDU are achieved on DRAM capacitor process. It
revealed strong relation to development parameter setting. Furthermore, specific pattern formation considering optical
items, ex: OPE, NRF (non-resolution feature) and interaction between double exposure have also been analyzed and
difficulties of generating a specific pattern with negative tone resist double exposure have been figured out.
We have developed a very simple source optimization (SO) method for L/S and C/H critical layers patterning of
advanced NAND FLASH. Starting from the strong off-axis illumination shape which is optimized for the finest
structure of the mask pattern, a systematic procedure is performed to extract the optimum parameters of additional assist
sources to balance the imaging performance (DOF, contrast and optical proximity effect, etc.) of dense/sparse/rough
patterns. Performance equations (linear optimization) with performance map (sensitivity) are utilized to search the best
combination of intensity for each assist source. For C/H pattern, the optimization procedure is modified to solve the
non-linearity and non-continuity problems on the relationship between assist source intensity and each imaging
performance. Finally, optimized source shapes have been successfully demonstrated and verified on 40 nm node NAND
FLASH L/S and C/H critical patterns despite the simplicity of the optimization method, without utilizing SO dedicated
Self Aligned Double Patterning (SADP) has the advantage of dense array definition with good pitch control and is hence
useful for memory devices; but its feasibility of two-dimensional circuit patterns definition is restricted on the other hand.
In SPIE 2009, we had proposed the ideas of 30nm node NAND FLASH cell circuit critical feature (pickup, gate, contact
array) decomposition by SADP, based on manual design. The concerns of process integration as well as SADP
alignment algorithm for each mask step were investigated and countermeasures were presented.
In this paper, the previous works on manual-based pattern decomposition are extended to a more sophisticated use on
full-area NAND FLASH critical layer layout decomposition by utilizing an automated electronic design (EDA) tool.
The decomposition tool together with OPC and simulation tools are integrated to optimize the lithographic performance
of local critical patterns in each decomposed mask step, and comparisons have been made as well to investigate the
differences in layout splitting algorithm between EDA-based and manual-based decomposition. Finally, the full-area
(9350×12800um) layout decomposition has been successfully demonstrated on NAND FLASH Gate and Metal critical layers by using the EDA tool with improved 2D structure handling algorithms.
Double patterning technology (DPT) is the best alternative to achieve 3x NAND flash node by 193nm immersion
lithography before entering EUV regime. Self-aligned double patterning (SADP) process is one of several DPT
approaches, and most likely be introduced into NAND flash manufacture. The typical single exposure process in
40nm node flash will become into multiple exposure job in 32nm node by DPT or SADP, and the overlay control
among these multiple exposure will be highly restricted than single exposure process. To reach tight overlay spec.
mainly relies on the contribution of alignment system of scanner, but the well alignment mark design with high
contrast signal and outstanding sustainability are essential factor as well. Typically, the feature size patterned in
SADP around 3x nm that is too narrow to form essential signals that is qualified to be the alignment mark and the
overlay mark either. This paper, we will discuss 1. the performance of alignment algorithm on direct alignment and
indirect alignment 2. different alignment mark design and 3. film scheme dependence (layer dependence). And
experiment result show the new mark design performs sufficient contrast and signal for subsequent layer aligning
As IC manufacturing goes from 45nm to 30nm node half-pitch, the lithography process k1 factor will fall below 0.25 by
using water-based ArF-immersion scanner. To bridge the gap between ArF-immersion and next generation lithography,
which is not ready yet for production, Double Patterning Technology (DPT) has been evaluated and identified as a
promising solution as it utilizes existing equipment and processes. Self Aligned Double Patterning (SADP) has the
advantage of dense array definition without overlay issue and is hence useful for memory device; but its characteristic
restricts the feasibility of two-dimensional circuit pattern definition on the other hand.
This paper describes the ideas of 30nm node NAND FLASH cell circuit critical feature (pickup, gate, contact array)
definition by decomposing the target patterns to SADP defined dense array in conjunction with cropping and/or
periphery masks steps. The concerns and issues of cropping/periphery mask step process integration as well as SADP
alignment algorithm are investigated, and the countermeasures with alternative process schemes and novel frame designs
are presented. Finally, simulation prediction has shown that the capability of 30nm NAND FLASH critical features
patterning with depth of focus equal to or above 0.15um is expected at each mask step by ArF-dry lithography.
High NA (1.35) Immersion litho runs into the fundamental limit of printing at 40-45nm half pitch (HP). The next generation EUVL tool is known to be ready not until year 2012. Double patterning (DP) technology has been identified as the extension of optical photolithography technologies to 3xnm and 2xnm half-pitch for the low k1 regime to fill in the gap between Immersion lithography and EUVL. Self Aligned Double Patterning (SADP) Technology utilized mature process technology to reduce risk and faster time to market to support the continuation of Moore's Law of Scaling to reduce the cost/function. SADP uses spacer to do the pitch splitting bypass the conventional double patterning (e.g. Litho-Freeze-Litho-Etch (LFLE), or Litho-Etch-Litho-Etch (LELE)) overlay problem. Having a tight overlay performance is extremely critical for NAND Flash manufacturers to achieve a fast yield ramp in production. This paper describes the challenges and accomplishment of a Line-By-Spacer (LBS) SADP scheme to pattern the 29nm half-pitch NAND Flash STI application. A 193nm Dry lithography was chosen to pattern on top of the amorphous carbon (a-C) film stack. The resist pattern will be transferred on the top a-C core layer follow by spacer deposition and etch to achieve the pitch splitting. Then the spacer will be used to transfer to the bottom a-C universal hardmask. This high selectivity a-C hardmask will be used to transfer the 29nm half-pitch pattern to the STI. Good within wafer CD uniformity (CDU) <2nm and line width roughness (LWR) <2nm for the 29nm half-pitch NAND FLASH STI were demonstrated as the benefits using double amorphous carbon hardmask layers. The relationships among the photoresist CDs, CD trimming , as-deposited spacer film thickness, spacer width and the final STI line/core space/gap space CDs will also be discussed in this paper since patterning is combining both lithography performance with CVD and Etch process performance. Film selection for amorphous carbon and the complete DP hardmask scheme in terms of etching selectivity, optical properties and stress optimization was another key challenge to balance excellent litho alignment signal strength and straight pattern profiles without line bending effects. Etching efforts also played a very important roll to obtain pattern integrality under such a high aspect ratio (> 10) case through the whole SADP process. Finally, cost analysis for 193nm dry lithography SADP will be compared to 193nm Immersion lithography SADP.