This study describes variable-area diode data analysis of surface and bulk effects of HgCdTe infrared photodiodes
passivated with dual-layer CdTe/ZnS films. We attempt to present a general analytical relation between the zero-bias
resistance-area product and the perimeter-to-area ratio of the diodes by variable-area diode array test structures. We have
taken contributions into consideration from surface leakage between HgCdTe and passivant due to band bending, surface
generation currents in the depletion region close to the HgCdTe-passivant interface, and the bulk currents. The model we
use is based on the one put forward by Vishnu Gopal. The variable-area diode data analysis can be of great practical help
in identifying the various possible mechanism contributing to the surface leakage currents. Through data analysis and
curve fitting, we can also get some other useful parameters (like junction depth), which can be the reference to other
experiment results. The experimental samples we used range from 20μm to 200μm in size and include both square and
circular diode geometries. The conventional boron implantation was used to form the p-n junction and Au was used for
the metal pads. The insulating layers of CdTe and ZnS were both electron-beam evaporated at a rate of 1.3 Å/sec. The
fabricated diode test patterns were wire-bonded and packaged into a dewar system. I-V measurements were performed
using a Keithley 4200 parameter analyzer. The data analysis and curve fitting are all dealt with by MATLAB.
Through the results we can find that the surface leakage is nearly the same to the bulk current in diameter between
50~150μm, which indicate that surface leakage is still a dominating dark current in small dimension diode. The results
also showed that diodes from 50 to 150μm in size have better performance than the larger or smaller ones and this can be
explained by the limit of material imperfection and the limit of processing techniques.
HgCdTe infrared detector is designed to operate at cryogenic temperatures, so vacuum baking is a required process for
out-gassing in packaging of devices. As HgCdTe material, as well as ZnS passivation layer is sensitive to heat induced
changes, this process may be problematical for HgCdTe devices even at relatively low temperatures. We try to solve the
problems of heat instability by the fabrication of CdTe/ZnS double passivation layers. The effect of vacuum baking is
investigated through current-voltage (I-V) characteristics. We have compared the effects on devices with different
passivation layers. We have also compared the photodiodes fabricated on MBE grown HgCdTe on GaAs substrates and
LPE grown HgCdTe on CdZnTe. The devices were passivated with electron beam evaporated CdTe and ZnS and the p-n
junction was formed by ion-implantation. Through the analysis of I-V characteristics, we found that the devices
passivated with ZnS cannot afford vacuum baking even at 70°C, while the CdTe/ZnS- passivated devices can afford up
to 110°C temperature and the performance improved. After only 4 hours baking, the dynamic resistance of ZnS
passivation devices began to decrease and 10 hours later the zero-bias dynamic resistance (R0) decreased nearly 3 times.
Further baking of 110°C sees the maximum dynamic resistance of CdTe/ZnS passivation devices increase 2 to 4 times.
An insight into the mechanisms and parameters that are affected by vacuum baking is also gained by resistance-voltage
(R-V) curve fitting. The results also indicated the baking effects on LPE grown HgCdTe devices are almost same to
MBE grown HgCdTe devices.