Lithography simulation has proven to be a technical enabler to shorten development cycle time and provide direction
before next-generation exposure tools and processes are available. At the early stages of design rule definition for a new
technology node, small critical areas of layout are of concern, and optical proximity correction (OPC) is required to
allow full exploration of the 2D rule space. In this paper, we demonstrate the utility of fast, resist-model-based, OPC
correction to explore process options and optimize 2D layout rules for advanced technologies. Unlike conventional OPC
models that rely on extensive empirical CD-SEM measurements of real wafers, the resist-based OPC model for the
correction is generated using measured bulk parameters of the photoresist such as dissolution rate. The model therefore
provides extremely accurate analysis capability well in advance of access to advanced exposure tools. We apply this
'virtual patterning' approach to refine lithography tool settings and OPC strategies for a collection of 32-nm-node layout
clips. Different OPC decorations including line biasing, serifs, and assist features, are investigated as a function of NA
and illumination conditions using script-based optimization sequences. Best process conditions are identified based on
optimal process window for a given set of random layouts. Simulation results, including resist profile and CD process
window, are validated by comparison to wafer images generated on an older-generation exposure tool. The ability to
quickly optimize OPC as a function of illumination setting in a single simulation package allows determination of
optimum illumination source for random layouts faster and more accurately than what has been achievable in the past.
This approach greatly accelerates design rule determination.
Resist trimming is a technique that is often used to close the gap between line widths which can be
repeatedly printed with currently available lithography tools and the desired transistor gate length. For
the 65-nm node, the resist line width delivered at pattern is between 60 to 70 nm while the final transistor
gate length is usually targeted between 35 to 45 nm. The 15 to 35 nm critical dimension (CD) difference
can be bridged by resist trimming. Due to the stringent gate CD budget, a resist trimming process should
ideally have the following characteristics: i) no degradation in CD uniformity; ii) no damage in pattern
fidelity; iii) controllable CD trim rate with good linearity; and iv) no degradation in line edge roughness
(LER) or line width roughness (LWR).
Unfortunately, a realistic resist trimming process is never perfect. In particular, resist consumption and
the resultant internal stress build-up during resist trimming can lead to resist line bending. The effect of
bent resist lines is a higher post-etch CD and significantly degraded local CD uniformity (LCDU).
In order to reduce resist bending CD errors (defined as the difference between the post-etch CD and the
design CD due to resist bending after trimming) several useful procedures either in layout or in processes
are presented. These procedures include: i) symmetrically aligning gates to contact pads and field
connecting poly in the circuit layout; ii) enlarging the distance between contact pad (or field connecting
poly) to active area within the limits of the design rules (DR) and silicon real estate; iii) adding assist
features to the layout within the DR limits; iv) minimizing resist thickness; and v) applying special plasma
cure before resist trim.
How to effectively control the critical dimension (CD) is always a hot topic in photolithography. In 65nm node using phase shift mask (PSM) techniques, any factors related to CD variations should not be ignored without full investigation due to the ever-decreasing CD budget. In this paper, we focus on the local CD variation (LCDV) at the gate level within an area of 200μm x 200μm printed on a 193nm exposure tool. In contrast with AWLV (across wafer line variation) and ACLV (across chip line variation), the more localized LCDV implies that it is more dependent on the following three major factors: i) local wafer flatness mainly dominated by STI (shallow trench isolation) steps after CMP (chemical mechanical polishing); ii) effectiveness of OPC (optical proximity correction) covering all transistors with different geometrical shapes in circuit layout and iii) line edge roughness (LER) and line width roughness (LWR) related to photo and etch processes. Although OPC errors, LER and LWR are also very important, the current discussion will be limited in characterizing the relationship between LCDV and STI step-height (S-H) due to the length limitation. The STI S-H between the active surface and the trench oxide surface always exists due to the different material selectivity in the CMP process. The major gate CD influences from STI S-H are strongly correlated to the different geometrical shapes of transistors in circuits, such as single/multi-finger, wide/narrow, interior/exterior-flare and etc. According to our experiments and simulations from both alt-PSM (alternating PSM) and att-PSM (attenuating PSM) processes, the following important conclusions can be derived. a) The gate CDs in two PSM processes show different sensitivities to STI S-Hs in different geometrical shapes of transistors in circuit layout. The alt-PSM process is more sensitive than the att-PSM, especially for isolate gates. This is a shortcoming for the alt-PSM process in effectively controlling the LCDV. b) STI S-H usually makes the CD larger in both PSM processes, especially for the isolated gates in the alt-PSM process. From our observations, it is generally true that the narrower the transistor width, the higher the gate CD will be. However, CD variation trends in the att-PSM process are not so explicit as observed with alt-PSM. c) One should be very careful when trying to improve the CD uniformity by reducing STI step-height by using a blanket etch back because OPC errors are tightly combined with STI step-heights. d) Improving the STI S-H uniformity is always welcome because it will improve the AWLV. e) The narrow isolated gate is the best CD feature to monitor the interaction of AWLV with STI S-H uniformity.
The continuing shrinkage of device size will result in stringent demands on high precision CD control. For example, at 0.13um technology node a typical poly gate size variation should be controlled within +/- 8nm or even smaller. This tight CD budget includes all possible variations which can be from different modules of resist coating track, optical and mechanical parts of exposure tool, non-uniformity of wafer substrate, CD metrology, mask making and so on. Particularly, the residual swing effect after applying an inorganic anti-reflection layer (SiON) still can claim a significant CD budget if not properly optimized. Therefore, how to minimize the residual swing effect still plays important role in CD control. Simulation of reflectivity is considered analytically rigorous and is therefore frequently employed to aid in process development. However, since in manufacturing environments people usually pay more attention to the repeatability of optical metrology tools rather than their accuracies, it is not surprising if some significant discrepancies exist between theoretical and experimental results. Instead of discussing the detail error sources and the tool calibrations, a quick and convenient experimental methodology is introduced to account for such differences and to optimize the film stack composition effectively. In this paper, with the CD variations on metal and poly substrates as examples, an effective combination between the calculations and the experiments is presented in order to minimize the CD swing. We also demonstrate that with the "single wafer swing curve" technique, the residual swing effect can be easily detected and minimized. This methodology provides a possibility to determine the best anti-reflection layer not only from theoretical but also from experimental point of view in manufacturing environments. Since the residual swing effect is a common issue, the results of this paper can be widely used in either manufacturing fabs or experimental labs.
As transistor engineering continues to well below 100 nm length devices, ion implantation process tolerances are making these formerly "non-critical" lithography levels more and more difficult. In order to minimize the channeling effect and to obtain a controllable profile of dopant, an angled implantation is often required. However, a shadow area of resist pattern is always accompanied with an angled implantation. This shadowing effect consumes silicon real estate, and reduces the line edge placement (LEP) tolerances. Therefore, methodologies to reduce the shadowing effect in angled implantation become a critical consideration not only for device engineering but also for photolithography. Based on the model analysis, simulation and experiments, this paper presents an effective novel process utilizing dual-wavelength exposure (DWE) to reduce the shadowing effect. The DWE process is realized by two consecutive exposures for an I-line resist with a DUV stepper/scanner and an I-line stepper. The process leverages the high absorption coefficient of novalak-DNQ resist at 248 nm, and results in a tunable post-develop resist thickness to minimize the shadowing effect. It is effective in satisfying the junction requirements and also is helpful in minimizing the number of photoresists in a manufacturing fab. A repeatable resist profile and an excellent CD uniformity across wafer also indicated that the DWE is a potentially manufacturable process.
Swing curve generation is an important and common exercise in the design, characterization, and optimization of photolithography processes. The development of a robust anti-reflective strategy for a given process often necessitates multiple experimental iterations of the swing curve generation. The traditional methodology for generating a photoresist thickness swing curve plot is time and silicon intensive; usually involving processing and metrology on a dozen or more wafers. In addition, the resulting curve often can convolve systematic and random wafer-wafer effects due to other track/resist/scanner related variables. In some cases, such as very low reflectivity underlying substrate the signal to noise ratio is poor enough to effectively mask the sinusoidal swing behavior from visibility. In this paper, we present a new methodology to generate a swing curve by using a single wafer. The critical point of this method is to generate a temperature gradient on the wafer during the initial step of photoresist dispense and coating. Since the resist viscosity is inversely proportional to the temperature, a significant resist thickness variation can be produced across the wafer, which can easily encompass one swing period of thickness or more. The resulting resist thickness signature across the wafer is seen to be very repeatable, such that a companion wafer can be measured at multiple positions corresponding to CD metrology lcoations on the patterned wafer. The possibility of deconvolving systematic across wafer CD variability due to other process variables is discussed by characterizing a control wafer with conventional uniform resist thickness. Our experiments for I-line and DUV resists indicated that this method not only provides reliable swing curves but also saves photoresist, silicon, and time both for engineering and machine. Moreover, this methodology represents an improved signal to noise ratio such that makes it particularly useful for ARC thickness/composition optimization. Several examples utilizing this method will be presented.
Resist critical dimensions (CD) and thickness are usually obtained by in-line CD SEM or in-line optical metrology measurements but varification or calibration of these is typically achived by cross sectional SEM. As we push CDs to 100nm and beyound, descrepencies between these two sources data can constitute a large percentage of the target dimension. Particularly for 193nm resists, the CD shrinkage under SEM has been well characterized, but the vertical and horizontal compaction behavior in across sectional SEM has not been explored. In this paper, the discussion is divided into two parts. One is for bulk resist and another is for patterned resist. For bulk case, the the only variable is vertical thickness. The experiments for I-line, 248nm and 193nm resist indicated that the resist thickness from the cross sectional image is strongly dependent on the resist polymer structure, the SEM conditions and the interrogration time under SEM E-beam. Therefore, the thickness comparison between optical and electronic is not always meaningful because the cross sectional thickness often shows a low thickness than the optically determined value. We have determined the optimum SEM condition to minimize vertical compaction. There are two variables for patterned resist, vertical thickness and lateral CD size. Our experiments for I-line and 248nm resists exhibited that the patterned resist thickness can be 30% lower than the optical thickness. However, the lateral CD sizes showed less variation relative to the different SEM conditions. The unique behaviors of 193nm patterned resist are also displayed and discussed in this paper. Based on all experimental data, different SEM conditions are recommended based on different purposes to generate accurate cross sectional resist images.
Photolithography on reflective surfaces with topography can cause exposure in unwanted areas, resulting in the phenomenon of reflective notching. Solutions to this problem are known within the industry, including the use of bottom anti-reflective coatings (ARCs) and dyed photoresist. In certain situations, such as on implant layers, the use of a BARC may be impractical. One potential solution to this problem lies in optimization of the illumination settings. It is known that changes in the illumination settings NA and sigma have an impact on the swing curve amplitude. It will be shown that for certain situations, reflective notching can be virtually eliminated through proper selection of the illumination settings.
The reduced CD (critical dimension) of devices places more stringent requirements on the photo process for metal layers, especially for the metal local-interconnect (MLIC) or M0 layer, which can have a minimum dimension similar to poly-gate. This layer has shown a highly localized substrate contamination defect with chemically-amplified (CA) DUV photoresists, which is related to the underlying contact plug. The failure analysis shows that reducing this defect plays an import role in enhancing the yield of a SRAM used as a test vehicle in process development. After transistors are formed, contacts to gates and source/drain regions are opened and subsequently filled with W-plugs, then a PVD TiN film is deposited as a MLIC layer between transistors. A silicon oxynitride (SiON) film is deposited as an anti-reflection layer, and a SiO2 cap is utilized as a substrate contamination barrier. However, with such a film structure, after resist patterning etch and cleaning, one major defect was often observed at the final inspection stage. This defect was always spatially-correlated to an underlying contact plug, and resulted in highly localized 'swelling' or bridging of adjacent photoresist features. In this paper, the MLIC swelling defect is characterized and its possible root causes are discussed. The correlation between the defect and the type of resist (high activation energy and low activation energy) is investigated as well. In order to eliminate the defect thoroughly or to reduce the number of defects substantially, many experimental tests have been carried out, which include the defectivity comparisons with different resists, the application of an organic bottom anti-reflection coating (BARC), the outgas reduction for poly-metal dielectric (PMD) layers, the optimization of resist striping procedure for implant layer before metal deposition, the double CA resist coating and so on. The results indicate that it is possible to eliminate the swelling defect at the photo stage by applying several special treatments.