In this paper, a method that adds an inverse taper at the endface of the waveguide is analyzed to reduce the silicon waveguide endface reflection (SWER). A high index-contrast optical waveguide on a silicon-on-insulator (SOI) wafer allows for the strong optical confinement, while it also brings in a substantial endface reflection. Most parameters of the taper, such as the length and tip width of the taper, and wavelength of the guided light, even the shape of the taper, have been studied in detail using the three-dimensional finite-difference time-domain (3D-FDTD) method to reduce the SWER. In addition, we have also proposed a new structure that adds the special taper to the straight-through port of the 3-dB directional coupler (DC) to measure the SWER in experiments. The experimental results show good agreement with our simulation results. This taper is useful and small enough that can be applied to many silicon photonic devices and large scale photonic integration circuits (PICs).
In this work, we design and fabricate a highly compact third-order racetrack add-drop filter consisting of silicon waveguides with modified widths on a silicon-on-insulator (SOI) wafer. Compared to the previous approach that requires an exceedingly narrow coupling gap less than 100nm, we propose a new approach that enlarges the minimum feature size of the whole device to be 300 nm to reduce the process requirement. The three-dimensional finite-difference time-domain (3D-FDTD) method is used for simulation. Experiment results show good agreement with simulation results in property. In the experiment, the filter shows a nearly box-like channel dropping response, which has a large flat 3-dB bandwidth (~3 nm), relatively large FSR (~13.3 nm) and out-of-band rejection larger than 14 dB at the drop port with a footprint of 0.0006 mm<sup>2</sup> . The device is small and simple enough to have a wide range of applications in large scale on-chip photonic integration circuits.