Dr. Ying Zhang
SPIE Involvement:
Conference Program Committee | Author | Editor | Instructor
Publications (8)

Proceedings Article | 27 April 2017 Presentation
Proceedings Volume 10149, 101490C (2017) https://doi.org/10.1117/12.2261801
KEYWORDS: Image processing, 3D metrology, 3D image processing, Image quality, Lithium, Etching, Lithography, Metrology, Oxides, Digital imaging

Proceedings Article | 27 April 2017 Presentation
Regina Freed, Uday Mitra, Ying Zhang
Proceedings Volume 10149, 1014905 (2017) https://doi.org/10.1117/12.2261107
KEYWORDS: Etching, Error analysis, Transistors, Optical lithography, Immersion lithography, Nanotechnology, Nanostructures, Current controlled current source

Proceedings Article | 28 March 2016 Paper
Shimon Levi, Ishai Schwarzband, Roman Kris, Ofer Adan, Elly Shi, Ying Zhang, Kevin Zhou
Proceedings Volume 9782, 97820I (2016) https://doi.org/10.1117/12.2220814
KEYWORDS: Line edge roughness, Etching, Line width roughness, Scanning electron microscopy, Edge roughness, Optical lithography, Signal to noise ratio, Statistical analysis, Lithography, Stochastic processes

Proceedings Article | 23 March 2016 Paper
L. Dorf, J.-C. Wang, S. Rauf, Y. Zhang, A. Agarwal, J. Kenney, K. Ramaswamy, K. Collins
Proceedings Volume 9782, 97820J (2016) https://doi.org/10.1117/12.2222309
KEYWORDS: Etching, Plasma etching, Plasma, Ions, Silicon, Tellurium, Plasma systems, Chlorine, Chemical species, Electron beams

SPIE Journal Paper | 23 December 2013 Open Access
JM3, Vol. 12, Issue 04, 041301, (December 2013) https://doi.org/10.1117/12.10.1117/1.JMM.12.4.041301
KEYWORDS: CMOS technology, Optical lithography, Plasma etching, Etching, Plasma, Semiconductors, Lithography, Extreme ultraviolet, Line edge roughness, Directed self assembly

Showing 5 of 8 publications
Proceedings Volume Editor (2)

SPIE Conference Volume | 16 April 2013

SPIE Conference Volume | 16 April 2012

Conference Committee Involvement (14)
Advanced Etch Technology and Process Integration for Nanopatterning XIV
23 February 2025 | San Jose, California, United States
Advanced Etch Technology and Process Integration for Nanopatterning XIII
26 February 2024 | San Jose, California, United States
Advanced Etch Technology and Process Integration for Nanopatterning XII
28 February 2023 | San Jose, California, United States
Advanced Etch Technology and Process Integration for Nanopatterning XI
26 April 2022 | San Jose, California, United States
Advanced Etch Technology and Process Integration for Nanopatterning X
22 February 2021 | Online Only, California, United States
Showing 5 of 14 Conference Committees
Course Instructor
SC992: Lithography Integration for Semiconductor FEOL & BEOL Fabrication
Semiconductor wafer fabrication, traditionally including Front-End-Of-The-Line (FEOL), Middle-Of-The-Line, (MOL), and Back-End-Of-The-Line (BEOL), constitutes the entire process flow for manufacturing modern computer chips. The typical FEOL processes include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL is mainly gate contact formation, which is an increasingly challenging part of the whole fabrication flow, particularly for lithography patterning. The BEOL processes include dielectric film deposition, patterning, metal fill and planarization by chemical mechanical polishing. The state-of-the-art semiconductor chips, the so called 5 nm node of Complementary Metal–Oxide–Semiconductor (CMOS) chips, in mass production features the fifth generation three-dimensional (3D) FinFET, a minimum metal pitch of about 28 nm and copper (Cu)/low-k interconnects. It is the second generation of logic chips fabricated with extreme ultra-violet (EUV) lithography. The Cu/low-k interconnects are fabricated predominantly with a dual damascene process using plasma-enhanced CVD (PECVD) deposited interlayer dielectric (ILDs), PVD Cu barrier and electrochemically plated Cu wire materials. Successful fabrication and qualification of modern semiconductor chip products requires a deep understanding of the intricate interplay between the materials and the processes employed. This course provides an overview of modern semiconductor wafer fabrication process flow, its integration schemes, fabrication unit processes and key factors affecting yields. It highlights unique challenges in lithography for FEOL, MOL and BEOL and discusses potential solutions as well as practical techniques. The goal of this course is to provide materials, process, integration and lithography engineers with a fundamental basis to develop materials and processes for FEOL, MOL and BEOL patterning and to trouble shoot fabrication problems. This course will also introduce new materials (such as high mobility channel materials, high-K/metal gate or HKMG, III-V materials, non-copper BEOL metals), new device and interconnect structures (such as, gate-all-around transistor, FinFET/ Trigate, nanowires, self-aligned via integration, Cu/air-gap interconnects, buried power rails, PowerVia) and new integrations (such as 3D IC, Through-Silicon Via or TSV, 3D heterogeneous integration, hybrid bonding) as well as recent advances in lithography technology (such as double patterning, EUV lithography, high-NA EUV and directed self-assembly, DSA). Implications of these FEOL, MOL and BEOL technologies for lithography will be discussed.
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