Dr. Ying Zhang
at Applied Materials Inc
SPIE Involvement:
Conference Program Committee | Author | Editor | Instructor
Publications (8)

Proceedings Article | 27 April 2017 Presentation
Proc. SPIE. 10149, Advanced Etch Technology for Nanopatterning VI
KEYWORDS: Oxides, Lithography, Metrology, Lithium, Etching, Image processing, Image quality, Digital imaging, 3D metrology, 3D image processing

Proceedings Article | 27 April 2017 Presentation
Proc. SPIE. 10149, Advanced Etch Technology for Nanopatterning VI
KEYWORDS: Nanotechnology, Nanostructures, Optical lithography, Etching, Error analysis, Transistors, Immersion lithography, Current controlled current source

Proceedings Article | 28 March 2016 Paper
Proc. SPIE. 9782, Advanced Etch Technology for Nanopatterning V
KEYWORDS: Signal to noise ratio, Lithography, Optical lithography, Statistical analysis, Etching, Scanning electron microscopy, Line width roughness, Line edge roughness, Stochastic processes, Edge roughness

Proceedings Article | 23 March 2016 Paper
Proc. SPIE. 9782, Advanced Etch Technology for Nanopatterning V
KEYWORDS: Electron beams, Etching, Chemical species, Ions, Silicon, Plasma etching, Chlorine, Tellurium, Plasma systems, Plasma

SPIE Journal Paper | 23 December 2013
JM3 Vol. 12 Issue 04
KEYWORDS: CMOS technology, Optical lithography, Plasma etching, Etching, Plasma, Semiconductors, Lithography, Extreme ultraviolet, Line edge roughness, Directed self assembly

Showing 5 of 8 publications
Proceedings Volume Editor (2)

SPIE Conference Volume | 16 April 2013

SPIE Conference Volume | 16 April 2012

Conference Committee Involvement (10)
Advanced Etch Technology and Process Integration for Nanopatterning X
21 February 2021 | San Jose, California, United States
Advanced Etch Technology for Nanopatterning IX
25 February 2020 | San Jose, California, United States
Advanced Etch Technology for Nanopatterning VIII
25 February 2019 | San Jose, California, United States
Advanced Etch Technology for Nanopatterning VII
26 February 2018 | San Jose, California, United States
Advanced Etch Technology for Nanopatterning VI
27 February 2017 | San Jose, California, United States
Showing 5 of 10 Conference Committees
Course Instructor
SC992: Lithography Integration for Semiconductor FEOL & BEOL Fabrication
Semiconductor fabrication, traditionally including Front-End-Of-The-Line (FEOL), Middle-Of-The-Line, (MOL), and Back-End-Of-The-Line (BEOL), constitutes the entire process flow for manufacturing modern computer chips. The typical FEOL processes include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL is mainly gate contact formation, which is an increasingly challenging part of the whole fabrication flow, particularly for lithography patterning. The BEOL processes include dielectric film deposition, patterning, metal fill and planarization by chemical mechanical polishing. The state-of-the-art semiconductor chips, the so called 7 nm node of Complementary Metal–Oxide–Semiconductor (CMOS) chips, in mass production features the fourth generation three dimensional (3D) FinFET, a minimum metal pitch of about 40 nm and copper (Cu)/low-k interconnects. It is the first generation of logic chips fabricated with extreme ultra-violet (EUV) lithography. The Cu/low-k interconnects are fabricated predominantly with a dual damascene process using plasma-enhanced CVD (PECVD) deposited interlayer dielectric (ILDs), PVD Cu barrier and electrochemically plated Cu wire materials. Successful fabrication and qualification of modern semiconductor chip products requires a deep understanding of the intricate interplay between the materials and the processes employed. This course provides an overview of modern semiconductor fabrication process flow, its integration schemes, fabrication unit processes and key factors affecting yields. It highlights unique challenges in lithography for FEOL, MOL and BEOL and discusses potential solutions as well as practical techniques. The goal of this course is to provide materials, process, integration and lithography engineers a fundamental basis to develop materials and processes for FEOL, MOL and BEOL patterning and to trouble shoot fabrication problems. This course will also introduce new materials (such as high-K/metal gate or HKMG, III-V materials, non-copper BEOL metals), new device and interconnect structures (such as FinFET/ Trigate, nanowires, self-aligned via integration, Cu/air-gap interconnects) and new integrations (such as 3D IC, Through-Silicon Via or TSV, 3D heteogeneous integration) as well as recent advances in lithography technology (such as double patterning, EUV lithography and directed self-assembly, DSA). Implications of these FEOL, MOL and BEOL technologies for lithography will be discussed.
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