A prescaler is widely used in frequency synthesizers in order to handle channel selection. The division ratio has to be chosen carefully to achieve the desired frequency. In this paper, we present a 6 modulus prescaler in a 0.18 μm SiGe BiCMOS technology. The prescaler is part of a 60 GHz frequency synthesizer. In addition, we present a frequency planning for the 60 GHz frequency synthesizer. The prescaler employs an integer-<i>N</i> architecture. The circuit has a programmable divider with a division ratio of 7 and 8 and two counters to control the division ratio. The programmable divider utilizes ECL circuits, while the counters utilise CMOS circuits. Therefore an ECL-to-CMOS converter is used to bridge these two kinds of circuits. Simulation results show that the prescaler operates up to 4 GHz from a 1.8 V supply voltage.
Phased array antennas have a large number of civilian and military applications. In this paper we briefly review common
approaches to an integrated implementation of radar and electronic warfare digital phase array module and highlight features
that are common to both of these applications. Then we discuss how the promising features of the radio frequency
integrated circuit (RFIC)-based technology can be utilized in building a transceiver module that meets the requirements
of both radar and electronic warfare applications with minimum number of external components. This is achieved by
researching the pros and cons of the different receiver architectures and their performance from the targeted applications
point of view. Then, we survey current RFIC technologies and highlight the pros and cons of these technologies and how
they impact the performance of the discussed receiver architectures.
High speed frequency dividers are critical parts of frequency synthesisers in wireless systems. These dividers
allow the output frequency from a voltage controlled oscillator to be compared with a much lower external
reference frequency that is commonly used in these synthesisers. Common trade-offs in high frequency dividers
are speed of division, power consumption, real estate area, and output signal dynamic range. In this paper
we demonstrate the design of a high frequency, low power divider in 0.18 µm SiGe BiCMOS technology. Three
dividers are presented, which are a regenerative divider, a master-slave divider, and a combination of regenerative
and master-slave dividers to perform a divide-by-8 chain. The dividers are used as part of a 60 GHz frequency
synthesizer. The simulation results are in agreement with measured performance of the regenerative divider.
At 48 GHz the divider consumes 18 mW from a 1.8 V supply voltage. The master-slave divider operates up to
36 GHz from a very low supply voltage, 1.8 V. The divide-by-8 operates successfully from 40 GHz to 50 GHz.
The design of common source (CS) Low Noise Amplifiers (LNA) for wireless receivers is presented. The design trade-offs between main criteria are discussed. An extra gate-to-source capacitor is added to the input transistor to reduce the transistor dimension while still satisfying the noise matching. The small MOSFET also improves the LNA linearity with comparatively small drain-source current. The extra gate-to-source capacitor is introduced by the bonding-pad parasitic capacitor; hence a negative effect parasitic capacitance is turned into a useful capacitor. The simulated Noise Figure (NF) of two single-ended LNAs using 0.18 μm CMOS process achieve 0.62 dB and 0.92 dB at 2.4 GHz and 5.25 GHz respectively while matching a 50 ohm impedance.
This paper presents the design of a 1 GHz continuous-time second order Lowpass Sigma Delta Modulator (LPSDM). The design is intended to meet the future requirements of wideband wireless receivers. The continuous-time Noise Transfer Function (NTF) for the modulator is realized using two <i>G<sub>m</sub></i>-<i>C</i> integrators with negative transconductance feedback and three linearized <i>G<sub>m</sub></i> elements. A three-stage delayed comparator is employed for designing the one bit quantizer, therefore a delayed NTF had to be synthesized. The presented target design is 0.18μm CMOS process. The designed chip uses both 3.3V and 1.8V MOSFETs and consumes 80mW including the clock driver and the output buffer. The performance of the modulator based on post layout simulation is 11 bits for a 5 MHz bandwidth and 8.6 bits for an 11MHz bandwidth.
In wideband surveillance and digital radio systems, there is a need to sweep the centre fequency of the data converter to detect a broadcast i nthe band of interest. Hence there is a need to design data converters with variable centre frequencies. Sigma-Delta modulators with programmable center frequency are chosen for this purpose. In this paper new resonators for a variable centre frequency bandpass Sigma-Delta modulator are presented. The new resonators have a centre frequency that extends from very low frequency up to half the sampling frequency. Simulation results of a fourth order discrete-time bandpass modulator employing the new resonator are presented using MATLAB and SPICE.