With ever increasing linewidth challenges per technology changes, the mask manufacturing process becomes more and more difficult. The challenges can be separated into two categories: image size and defects. Mask inspection detects hard defects most likely caused somewhere in the mask manufacturing process. Defect partitioning highlights the hard defects sources. They range from pre-exposure mask blank handling to the cleanliness of the process tools. A test vehicle was designed to allow for mask manufacturing defect partitioning via a die-to-die inspection tool. The process changes implemented range from pre-write mask handling to tool modifications. The methodology used to determine the process induced defects and the yield gains by making the necessary process changes will be presented.
Improvements in mask making techniques and metrology strategies have been required to satisfy the requirements of the 90nm technology node. With decreasing k1 and increasing MEF, critical dimension uniformity and defect specifications have faced severely tightened requirements. Many of the mask making process enhancements inspired by the 90nm node can be retrofitted into the 130nm node which improves mask quality as well as wafer-level performance. Mask critical dimension uniformity improvements directly impact wafer across chip linewidth variation which results in significantly improved chip performance. Specific examples of 130nm chip performance improvement will be discussed. Mask critical dimension and defect density improvements also result in improved mask yield and reduced mask costs. Driving 90nm mask process learning back into 130nm mask production significantly improves 130nm performance. Close interaction with the wafer lithography team allows focus on critical process window improvements for both the mask maker and wafer lithographer and allows rapid implementation of high-end process learning into older technologies.