As 3D NAND devices increase memory density by adding layers, scaling and increasing bits-per-cell, new overlay (OVL) metrology challenges arise. On product overlay (OPO) may decrease for critical thick layers such as thick deck-to-deck alignment, whereas high aspect ratio (Z-axis) structures introduce stress, tilt and deformation that require accurate and robust OVL measurements. Advanced imaging metrology (AIM®) targets, that consist of two side-byside periodic gratings in the previous and current layers, are typically used to measure OVL with Imaging Based Overlay (IBO) metrology systems. In this paper, we present a new approach that utilizes the Talbot effect in AIM to produce multiple contrast planes along the Z-axis, which enables a common focus position for both layers at a similar focus plane, resulting in improved measurement robustness. We will present Talbot effect theory, target design steps by metrology target design (MTD) simulator, actual measurement results on an advanced 3D NAND device and conclusions for such targets.
We show that an overlay (OVL) metrology system based on a scanning electron microscope can achieve accurate registration of buried and resist (top) structures. The positions were determined by both Back Scattered Electrons (BSE) and Secondary Electrons (SE). The accuracy was quantified for After-Development Inspection (ADI) of an advanced EUVL process. Results by linear tracking showed accuracy below 0.4nm, robust across process variation and target designs. The influence of various measurement conditions, e.g. Field of View, on position and OVL tracking was negligible. The measurement methodology presented is applicable for both standalone High Voltage SEM (HV-SEM) registration targets and optical targets, such as the Advanced Imaging Metrology (AIM®) target used by Imaging Based Overlay (IBO) metrology systems. Using SEM ADI OVL results as a calibration for optical overlay metrology tools we can demonstrate significant improvements in the optical ADI OVL accuracy on small targets like AIM in-die (AIMid).
On product overlay (OPO) challenges continue to be yield limiters for most advanced technology nodes, requiring new and innovative metrology solutions. In this paper we will cover an approach to boost accuracy and robustness to process variation in imaging-based overlay (IBO) metrology by leveraging optimized measurement conditions per alignment layer. Results apply to both DUV and EUV lithography for advanced Logic, DRAM, 3D NAND and emerging memory devices. Such an approach fuses multi-signal information including Color Per Layer (CPL) and focus per layer. This approach with supporting algorithms strives to identify and address sources of measurement inaccuracy to enable tight OPO, improve accuracy stability and reduce overlay (OVL) residual error within the wafer and across lots. In this paper, we will present a theoretical overview, supporting simulations and measured data for multiple technology segments. Lastly, a discussion about next steps and future development will take place.
Proc. SPIE. 11325, Metrology, Inspection, and Process Control for Microlithography XXXIV
KEYWORDS: Metrology, Optical parametric oscillators, Optical design, Overlay metrology, 3D acquisition, 3D metrology, Integrated circuits, Manufacturing, Logic, Process control
On product overlay (OPO) shrink is a key enabler to achieve high yield in integrated circuit manufacturing. One of the key factors to enable accurate measurement on grid (target) is the use of optimized overlay (OVL) mark design to achieve low OPO. The OVL mark design enables accurate and robust OVL metrology and improves measurability and basic performance requirements such as total measurement uncertainty (TMU). In this paper, we demonstrate the methodology of mark design for different devices based on simulations, measurements and verification. We compare OVL performance of AIM® targets and grating-over-grating imaging targets utilizing the Moiré effect. Methodologies described in this work utilize robust AIM (rAIM™) targets, target design from the MTD AcuRate™ simulation-based OVL metrology target design tool, and the Archer™ OVL metrology system.
For today’s advanced processes, in order to achieve higher optical lithography resolution, some of the layers require extreme dipole illumination conditions. One example is the modern DRAM process, where numerous critical layers are patterned with extreme dipole scanner illumination. Conventional (both imaging-based and diffraction-based) overlay marks on such layers typically use horizontal or vertical lines that suffer from insufficient accuracy in overlay device tracking. The new Diagonal AIM (DAIM™) overlay mark mimics the actual device through the usage of tilted structures. Significant improvement in device overlay tracking was demonstrated using the DAIM overlay mark.
Tool induced shift (TIS) is a measurement error attributed to tool asymmetry issues and is commonly used to measure the accuracy of metrology tools. Overlay (OVL) measurement inaccuracy is commonly caused by lens aberration, lens alignment, illumination alignment and asymmetries on the measured target. TIS impacts total measurement uncertainty (TMU) and tool-to-tool matching, and TIS variation across wafer can account for inaccuracy, if not fully corrected, as it depends on the incoming process condition. In addition, both lot-to-lot and wafer-to-wafer process variation are influenced by TIS in terms of overlay performance, which also includes metrology tool-to-tool efficiency in terms of throughput. In the past, TIS correction was only done using a small sampling, resulting in additional error in the measurement which was not corrected. Hence, a new methodology is explored to improve overlay measurement accuracy by Modeled-TIS (M-TIS). This paper discusses a new approach of harnessing Machine Learning (ML) algorithms to predict TIS correction on imaging-based overlay (IBO) measurements at the after-develop inspection (ADI) step. KLA’s ML algorithm is trained to detect TIS error contributors to overlay measurements by training a model to find the required TIS correction for one wafer. This information, along with additional accuracy metrics, is then used to predict the TIS for other wafers, without having to actually measure the wafers. In this paper, we present the results of a case study focusing on DRAM and 3D NAND production lots.
On product overlay (OPO) challenges are quickly becoming yield limiters for the latest technology nodes, requiring new and innovative metrology solutions. In this paper we will cover current and future overlay trends in logic and memory device processing. We will review new lithography overlay challenges and node-after-node trends in the OPO error budget for advanced logic, DRAM, and 3D NAND devices. The central question of this paper is whether optical overlay metrology can keep up with challenges that include accuracy, intra-field variability, target-to-device offset, and others. After surveying the two dominant technologies in optical overlay metrology (IBO and SCOL®), we will outline innovative solutions that will help to address metrology challenges for the new device nodes.
In the latest 3D NAND devices there is a larger focus on measurement accuracy control, coupled with more traditional minimization of Total Measurement Uncertainty (TMU). Measurement inaccuracy consumes an increasingly significant part of the overlay (OVL) budget, requiring control and optimization.
In this paper we will show the improvement in imaging OVL measurement accuracy using wave tuning (WT) capability combined with advanced algorithms to address 3D NAND process challenges. In addition to new OVL target designs that take advantage of WT capability, we also demonstrate improvement in OVL model residuals through optimization of measurement bandwidth, focus position and number of grab frames. Improvements in precision and tool-to-tool matching are also realized through both optimization of the region of interest (ROI) and splitting measurement areas using a dual-recipe technique.
This paper presents multispectral active gated imaging in relation to the transportation and security fields. Active gated imaging is based on a fast gated camera and pulsed illuminator, synchronized in the time domain to provide range based images. We have developed a multispectral pattern deposited on a gated CMOS Image Sensor (CIS) with a pulsed Near Infrared VCSEL module. This paper will cover the component-level description of the multispectral gated CIS including the camera and illuminator units. Furthermore, the design considerations and characterization results of the spectral filters are presented together with a newly developed image processing method.
Proc. SPIE. 9407, Video Surveillance and Transportation Imaging Applications 2015
KEYWORDS: Imaging systems, Image sensors, Near infrared, Sensors, Cameras, Fiber optic illuminators, Gated imaging, Safety, Night vision, Control systems
The paper presents the Active Gated Imaging System (AGIS), in relation to the automotive field. AGIS is based on a fast gated-camera equipped with a unique Gated-CMOS sensor, and a pulsed Illuminator, synchronized in the time domain to record images of a certain range of interest which are then processed by computer vision real-time algorithms. In recent years we have learned the system parameters which are most beneficial to night-time driving in terms of; field of view, illumination profile, resolution and processing power. AGIS provides also day-time imaging with additional capabilities, which enhances computer vision safety applications. AGIS provides an excellent candidate for camera-based Advanced Driver Assistance Systems (ADAS) and the path for autonomous driving, in the future, based on its outstanding low/high light-level, harsh weather conditions capabilities and 3D potential growth capabilities.
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