Extreme ultraviolet lithography (EUVL) is entering an industry production phase for 7nm logic and is under development for next node logic and memory applications. A key benefit of EUVL for logic interconnect lithography comes from the ability to pattern the metal layer at aggressive pitch using a single exposure. We report here a mask process compatible with a 30nm pitch patterning module for the demanding sub 7nm node, single expose interconnect application. We found a large increase in mask to wafer image transfer sensitivity during the 32nm to 30nm pitch shrink development that led to increases in stochastic and systematic wafer defect generation mechanisms. In this work, we describe our steps to characterize, model and improve the mask related factors that reduce this sensitivity as part of a successful 30nm pitch patterning module demonstration. High resolution wide area electron beam mask inspection alongside a suite of advanced mask characterization and optimization(AMCO)tools were key elements in understanding mask process gaps and improvement opportunities. Critical mask parameters optimized in closed loop with wafer response included two and three dimensional pattern fidelity, line roughness and spatial variability. Mask critical dimension targeting was found to be a critical factor for delivering the yielding 30nm pitch wafer process and this targeting was tuned dynamically through mask and wafer co-optimization. Finally, the role of wafer anchored process simulation proved an invaluable guide for linking various mask error source mechanisms to the wafer response.
Design weak points that have narrow process window and limits wafer yield, or hotspots, continue to be a major issue in semiconductor photolithography. Resolution enhancement techniques (RET) such as advanced optical proximity correction (OPC) techniques and source mask optimization (SMO) are employed to mitigate these issues. During yield ramp for a given technology node, full-chip lithography simulation, pattern-matching and machine learning are adopted to detect and remedy the weak points from the original design , . This is typically an iterative process by which these points are identified in short-loop lithography testing. Design retarget and/or OPC modifications are made to enhance process window until the yield goal is met. This is a high cost and time consuming process that results in a slow yield ramp for existing production nodes and increased time to market (TTM) for new node introduction. Local hotspot correction through mask and wafer harmonization is a method to enhance wafer yield with low cost and short cycle time compared to the iterative method. In this paper, a fast and low cost approach to hotspot correction is introduced. Hotspots were detected on wafer after OPC and characterized by using advanced mask characterization and optimization (AMCO) techniques. Lithographic simulations and AIMS measurement were used to verify the hotspot correction method. Finally, the validity of this new approach was evaluated by process window analysis and circuit probe yield test at wafer.
As nodes progress into the 7nm and below regime, extreme ultraviolet lithography (EUVL) becomes critical for all industry
participants interested in remaining at the leading edge. One key cost driver for EUV in the supply chain is the reflective
EUV mask. As of today, the relatively few end users of EUV consist primarily of integrated device manufactures (IDMs)
and foundries that have internal (captive) mask manufacturing capability. At the same time, strong and early participation
in EUV by the merchant mask industry should bring value to these chip makers, aiding the wide-scale adoption of EUV
in the future. For this, merchants need access to high quality, representative test vehicles to develop and validate their
own processes. This business circumstance provides the motivation for merchants to form Joint Development Partnerships
(JDPs) with IDMs, foundries, Original Equipment Manufacturers (OEMs) and other members of the EUV supplier
ecosystem that leverage complementary strengths. In this paper, we will show how, through a collaborative supplier JDP
model between a merchant and OEM, a novel, test chip driven strategy is applied to guide and validate mask level process
development. We demonstrate how an EUV test vehicle (TV) is generated for mask process characterization in advance
of receiving chip maker-specific designs. We utilize the TV to carry out mask process “stress testing” to define process
boundary conditions which can be used to create Mask Rule Check (MRC) rules as well as serve as baseline conditions
for future process improvement. We utilize Advanced Mask Characterization (AMC) techniques to understand process
capability on designs of varying complexity that include EUV OPC models with and without sub-resolution assist features
(SRAFs). Through these collaborations, we demonstrate ways to develop EUV processes and reduce implementation risks
for eventual mass production. By reducing these risks, we hope to expand access to EUV mask capability for the broadest
community possible as the technology is implemented first within and then beyond the initial early adopters.
Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for mask end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer’s process margin is shrinking at advanced nodes to a point that classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on sub-resolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. To overcome the limitation of 1D metrics, there are numerous on-going industry efforts to better define wafer-predictive metrics through both standard mask metrology and aerial CD methods. Even with these improvements, the industry continues to struggle to define useful correlative metrics that link the mask to final device performance. In part 1 of this work, we utilized advanced mask pattern characterization techniques to extract potential hot spots on the mask and link them, theoretically, to issues with final wafer performance. In this paper, part 2, we complete the work by verifying these techniques at wafer level. The test vehicle (TV) that was used for hot spot detection on the mask in part 1 will be used to expose wafers. The results will be used to verify the mask-level predictions. Finally, wafer performance with predicted and verified mask/wafer condition will be shown as the result of advanced mask characterization. The goal is to maximize mask end user yield through mask-wafer technology harmonization. This harmonization will provide the necessary feedback to determine optimum design, mask specifications, and mask-making conditions for optimal wafer process margin.
As device manufacturers progress through advanced technology nodes, limitations in standard 1-dimensional (1D) mask
Critical Dimension (CD) metrics are becoming apparent. Historically, 1D metrics such as Mean to Target (MTT) and
CD Uniformity (CDU) have been adequate for end users to evaluate and predict the mask impact on the wafer process.
However, the wafer lithographer’s process margin is shrinking at advanced nodes to a point that the classical mask CD
metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at
advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on subresolution
assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity.
These items are not quantifiable with the 1D metrology techniques of today. Likewise, the mask maker needs advanced
characterization methods in order to optimize the mask process to meet the wafer lithographer’s needs. These advanced
characterization metrics are what is needed to harmonize mask and wafer processes for enhanced wafer hot spot
analysis. In this paper, we study advanced mask pattern characterization techniques and their correlation with modeled
As optical lithography is extended into 10nm and below nodes, advanced designs are becoming a key challenge for mask
manufacturers. Techniques including advanced optical proximity correction (OPC) and Inverse Lithography
Technology (ILT) result in structures that pose a range of issues across the mask manufacturing process. Among the
new challenges are continued shrinking sub-resolution assist features (SRAFs), curvilinear SRAFs, and other complex
mask geometries that are counter-intuitive relative to the desired wafer pattern. Considerable capability improvements
over current mask making methods are necessary to meet the new requirements particularly regarding minimum feature
resolution and pattern fidelity. Advanced processes using the IMS Multi-beam Mask Writer (MBMW) are feasible
solutions to these coming challenges. In this paper, Part 2 of our study, we further characterize an MBMW process for
10nm and below logic node mask manufacturing including advanced pattern analysis and write time demonstration.