With each new technology node there is an increase in the number of layers requiring Optical Proximity Correction
(OPC) and verification. This increases the time spent on the mask tapeout flow which is already a lengthy portion of the
production flow. New technology nodes not only have additional layers that require OPC but most critical layers also
end up with more complex OPC requirements relative to previous generations slowing the tapeout flow even further. In
an effort to maintain acceptable turnaround time (TAT) more hardware resources are added at each node and electronic
design automation (EDA) suppliers are pushed to improve the software performance. The more we can parallelize
operations within the tapeout flow the more efficient we can be with the use of the CPU resources and drive down the
overall TAT. Traditional flows go through several cycles where data is broken up into templates, the templates are
distributed to compute farms for processing, pieced back together, and sometimes written to disk before starting the next
operation in the tapeout flow. During each of these cycles there are ramp up, ramp down, and input/output (I/O) times
that are incurred affecting the efficient use of hardware resources. This paper will explore the advantages of pipelining
the templates from one operation to the next in order to minimize these effects.
KEYWORDS: Optical components, Atrial fibrillation, Image processing, Image resolution, Photomasks, Optical proximity correction, System on a chip, Systems modeling, Model-based design, Process modeling
Demanding process window constraints have increased the need for effective assist feature placement algorithms that are robust and flexible. These algorithms must also allow for quick ramp up when changing nodes or illumination conditions. Placement based on the optical components of real process models has the potential to satisfy all of these requirements. We present enhancements to model-based assist feature algorithms. These enhancements include exploration of image-processing techniques that can be exploited for contact-via AF placement, model-based mask rule check (MRC) conflict resolution, the application of models to line-space patterns, and a novel placement technique for contact-via layers using a specially-built single modeling kernel.
As semiconductor manufacturing moves to the 90nm node and below, shrinking feature sizes and increasing IC complexity have combined to significantly stretch out the time needed to optimize and qualify process anchored OPC models and recipes. Process distortion and non-linearity become non-trivial issues and conspire to reduce the quality of the resulting corrections. Additionally, optimizing the OPC model and recipe on a limited set of test chip designs may not provide sufficient coverage across the range of designs to be produced in the process. Finally, the increased complexity of the transformation of the target pattern into a corrected mask pattern also increases the probability of system lithography errors. Fatal errors (pinch or bridge) or poor CD distribution may still occur. As a result, more than one reticle tape-out cycle is non uncommon to prove models and recipes that approach the center of process for a range of designs. In this paper, we describe a full-chip simulation based verification flow using a commercialized product that serves both OPC model and recipe development as well as post OPC verification after production release of the OPC.
As IC design rules shrink dramatically while the wavelength reduction in exposure systems can not keep up, extensive usage of Litho RET, Etch trimming and OPC techniques has become common practice in the integrated patterning flow. We examined a large number of CD measurement datasets of 90nm Contact layer ADI and AEI CD. As the etch bias is not a constant through pitch, AEI contribution has to be incorporated in the OPC model. Based on these datasets, we tried to develop a non-constant AEI model. In this paper, we investigated various strategies to streamline OPC modeling. Multiple regression method is used to fit CTR and CTE models. It was revealed that an extra long range Loading Kernel, additional to a well-fitted ADI model, may not successfully meet the fitting criteria we want. Mainly due to the fact that models with too many eigenvectors would have a tendency to over-fit-and-correct CD curves. We introduced an alternative approach by limiting the number of parameters in our model OPC algorithm. We achieved a 90nm Contact Model with OPC empirical data fitting error within +-2nm. Lastly, the wafer verification datasets showed only 3σ = 7.82 nm of through-pitch OPC residual error by using this Constant Threshold Etch Model, compared to simulation residue error 3σ of 8 nm.