While predicting and removing of lithographic hot-spots are a matured practice in recent semiconductor industry, it is
one of the most difficult challenges to achieve high quality detection coverage and to provide designer-friendly fixing
guidance for effective physical design implementation. In this paper, we present an accurate hot-spot detection method
through leveling and scoring algorithm using weighted combination of image quality parameters, i.e., normalized image
log-slope (NILS), mask error enhancement factor (MEEF), and depth of focus (DOF) which can be obtained through
lithography simulation. Hot-spot scoring function and severity level are calibrated with process window qualification
results. Least-square regression method is used to calibrate weighting coefficients for each image quality parameter.
Once scoring function is obtained with wafer results, it can be applied to various designs with the same process. Using
this calibrated scoring function, we generate fixing guidance and rule for the detected hot-spot area by locating edge bias
value which can lead to a hot-spot free score level. Fixing guidance is generated by considering dissections information
of OPC recipe. Finally, we integrated hot-spot fixing guidance display into layout editor for the effective design
implementation. Applying hot-spot scoring and fixing method to memory devices of the 50nm node and below, we could
achieve a sufficient process window margin for high yield mass production.
As the k1 factor of lithography process goes lower, model-based optical proximity correction (OPC) has become the most important step of post-tape-out data preparation for critical mask levels. To apply model-based OPC, a lithographic model with optical and resist parameters usually generated by a regression is required. It takes significant turn-around-time (TAT) to obtain the OPC model, normally more than 1 day per mask level. In this paper, we present an automatic and effective OPC model extraction method using the adaptive simulated annealing (ASA) algorithm. By applying this algorithm to extract the optimal model parameter values, we reduced the model parameter fitting time to less than 1 hour. We confirm the reliability and accuracy of the model generated by this method. With this newly developed automatic modeling method, we present a methodology to detect the critical failure on the wafer effectively that can occur by the focus variation during the lithography process. Generally, we sample only one set of measurement CD data taken under a controlled process condition with the best focus. Based on measurement data at the best focus, the in-house lithography simulator, FAITHTM, can generate simulated CD data for the multiple defocus levels without measurement data at the variable defocus levels. The multiple defocus models are built based on the simulated CD data and the automatic OPC modeling method makes the model buildings very fast. Finally, through the simulation of OPC result according to the multiple defocus models, we can verify or forecast the defocus effect before realistic patterning on wafers efficiently. We show the capability of weak point detection by this methodology on the 80nm DRAM devices with ArF photolithography.
To cope with sub-100nm technology in the mask making industry, a variable shaped e-beam(VSB) writing system is one of the solutions through its high-electron voltage. The VSB writing system, however, requires a different mask data preparation comparing to the traditional raster scan writing system. Due to the differences, mask making industries are confronted with difficult problems, such as explosively increasing data volume and unpredictably growing mask making time especially for memory devices. VSB system's writing time is determined by the conversion from CAD data to VSB data. The conversion time, especially for the critical layers of memory devices, mostly depends on to what extent optimize CAD data to enhance writing system throughput. For this reason, to shorten the unpredictably growing mask making time, a data conversion tool must consider the throughput of data conversion and mask writing at the same time. To reduce the data conversion time while retaining the optimal writing time, we propose the mixed-mode data processing method, in which the hierarchical data operation is applied on memory cells and the flat data operation is applied on peripheral circuits. For each area, different fracturing strategies are applied, too. The polygon-aware fracturing method is applied to improve the CD control within memory cells, and the selective one-directional fracturing method is applied to reduce the writing time within peripheral circuits.