Nanoimprint lithography (NIL) is a promising technique for fine-patterning with a lower cost than other lithography techniques such as EUV or immersion with multi-patterning. NIL has the potential of "single" patterning for both line patterns and hole patterns with a half-pitch of less than 20nm. NIL tools for semiconductor manufacturing employ die-by-die alignment system with moiré fringe detection which gives alignment measurement accuracy of below 1nm. <p> </p>In this paper we describe the evaluation results of NIL the overlay performance using an up-to-date NIL tool for 300mm wafer. We show the progress of both "NIL-to-NIL" and "NIL-to-optical tool" distortion matching techniques. From these analyses based on actual NIL overlay data, we discuss the possibility of NIL overlay evolution to realize an on-product overlay accuracy to 3nm and beyond.
Since multi patterning with spacer was introduced in NAND flash memory<sup>1</sup>, multi patterning with spacer has been a promising solution to overcome the resolution limit. However, the increase in process cost of multi patterning with spacer must be a serious burden to device manufacturers as half pitch of patterns gets smaller.<sup>2, 3</sup> Even though Nano Imprint Lithography (NIL) has been considered as one of strong candidates to avoid cost issue of multi patterning with spacer, there are still negative viewpoints; template damage induced from particles between template and wafer, overlay degradation induced from shear force between template and wafer, and throughput loss induced from dispensing and spreading resist droplet. Jet and Flash Imprint Lithography (J-FIL<sup>4, 5, 6</sup>) has contributed to throughput improvement, but still has these above problems. J-FIL consists of 5 steps; dispense of resist droplets on wafer, imprinting template on wafer, filling the gap between template and wafer with resist, UV curing, and separation of template from wafer. If dispensing resist droplets by inkjet is replaced with coating resist at spin coater, additional progress in NIL can be achieved. Template damage from particle can be suppressed by thick resist which is spin-coated at spin coater and covers most of particles on wafer, shear force between template and wafer can be minimized with thick resist, and finally additional throughput enhancement can be achieved by skipping dispense of resist droplets on wafer. On the other hand, spin-coat-based NIL has side effect such as pattern collapse which comes from high separation energy of resist. It is expected that pattern collapse can be improved by the development of resist with low separation energy.
It is getting harder to minimize feature size to satisfy bit growth requirement. 3D NAND flash memory has been
developed to meet bit growth requirement without shrinking feature size. To increase the number of memory cells per
unit area without shrinking feature size, we should increase the number of stacked film layers which finally become
memory cells. Wafer warpage is induced by the stress between film and wafer. Both of film stress and wafer warpage
increase in proportion to stacked film layers, and the increase of wafer warpage makes CD uniformity worse. Overlay
degradation has no relation with wafer warpage, but has indirect relation with film stress. Wafer deformation in film
deposition chamber is the source of overlay degradation. In this paper, we study the reasons why CD uniformity and
overlay accuracy are affected by film stress, and suggest the methods which keep CD uniformity and overlay accuracy
safe without additional processes.
Recently, we found a peculiar acid induced defect on chemically amplified photo resist applied to sub-
30nm NAND Flash Memory. This defect is like a hole-pattern with about 1um diameter, and induced by
diffusion of acid which makes photoresist soluble in developer, even though photoresist is not exposed
with KrF. With some experiment results, we found out that HCl gas, by-product of high temperature oxide
which is contained inside voids between two gate lines diffuses into photoresist through high temperature
oxide from voids, makes photoresist soluble in developer, and eventually creates the hole-type defect on
photoresist. To prevent this defect, we can suggest some methods which are substitution of KrF
photoresist into I-line photoresist, modification of oxide deposition recipe to suppress by-product, and
applying of non-CAR (Chemically Amplification Resist) type KrF photoresist not sensitive to acid.