The tight overlay budgets required for 45nm and beyond makes overlay control a very important topic. High order
overlay control (HOC) is becoming an essential methodology to remove the immersion induced overlay signatures.
However, to implement the high order control into dynamic APC system requires FA infrastructure modification and a
stable mass production environment. How to achieve the overlay requirement before the APC-HOC system becomes
available is important for RD environment and for product early ramp up phase. In this paper authors would like to
demonstrate a field-by-field correction (FxFc) or correction per exposure (CPE) methodology to improve high order overlay signature without changing current APC-linear control system.
The minimum design rule of device patterns for LSI implant layers has been shrinking constantly according to the
industry requirements. Wavelength has been shortened and numerical aperture (NA) of the scanner has been enlarged to
catch up with the required shrinkage. Implant layers are unique because the resist is nearly always used without an
antireflective coating, and as a result, the resist is in direct contact with a multitude of substrate materials. In implant
applications, the wafer topography sacrifices some of the lithographic performance in order to obtain adequate features
on both top and bottom of the topography. KrF lithography has applied to most of the ion implant levels at today's
To solve the several issues in ion implant process, New KrF resist was designed specifically for the lithographic /
implantation process requirements.
As the pattern size shrinking down below 1/4 of the exposure wavelength, the NA of exposure tool has to be increased
proportionally. The use of hyper NA and immersion exposure system for improving image quality may result in a
small workable process window. Hence, resolution enhancement technology (RET) becomes a necessity for
semiconductor manufacturing. Previous studies have demonstrated many RETs, such as CPL, DDL, IML and DPT etc.
can improve the process window for different applications.1,2,3,4 In this work, we show manufacturing
implementation of a 32nm node SRAM cell with different RET approaches. The diffusion, poly, contact, and metal
layers were chosen as the target design. The process development project starts from the wafer exposure scheme
setting, which includes the multi-exposure, illumination shape and mask type. After the RET has been specified, the
process performance indexes, such as MEEF, PW, and CDU are characterized by using both simulation and empirical
The mask design and OPC is implemented After the mask data preparation step, we then optimize exposure
parameters for best printing performance and follow it by verifying actual wafer data. The mask making spec and
DFM design rule constrains have been assessed and recommended for 32nm node manufacturing. Also, we have
examined the immersion process defect impact and control methodology for production environment. In this paper,
we report the result of optimizing RET process (including mask data generation, reticle making specifications, and
wafer printing) for 32nm SRAM. With 193nm ultra high NA immersion exposure scanner (such as ASML /1900), it
is capable of meeting 32nm SRAM manufacturing requirement.
As lithographic technology goes beyond the 45nm node, depth of focus (DOF) and
line width roughness (LWR) for poly gates have become critical parameters. There is a
growing interest in applying surface conditioner solutions during the post-develop
process to increase DOF and reduce LWR. Surface conditioners interact with resist
sidewall selectively, causing surface plasticization effect and smoothing the sidewall
profile. As a result, the LWR can be reduced and the poor pattern profile located in the
focus marginal area due to poor image contrast will be improved so that the depth of
focus (DOF) can be increased significantly. In this paper, the features of lines/spaces
patterned for the 45nm node by immersion lithography were used to evaluate surface
conditioner performance with regards to DOF increase and LWR reduction. The results
demonstrate there is about 1.5 nm LWR reduction, as well as a significant improvement
on the process window for DOF, for which there is 37.5% increase for ISO poly gates
and 36% increase for DENSE poly gates. No negative impact on the effect of optical
proximity correction (OPC) and resist profile were observed with the new process.
In addition, etch testing was conducted to determine how much post-develop LER
reduction has been retained through etch by comparing post-etch and post-develop LER
for both baseline and surface conditioner processes.
In this paper, we will demonstrate a novel approach to improve process window prediction capability. The new method, Lithography Manufacturability Check (LMC), will be shown to be capable of predicting wafer level CDs across an entire chip and the lithography process window with a CD accuracy of better than 10nm. The impact of reticle CD error on the weak points also will be discussed. The advantages of LMC for full chip process window analysis as well as the MEEF check to catch process weak points will be shown and the application to real designs will be demonstrated in this paper. LMC and MEEF checks are based on a new lithography model referred to as the Focus Exposure Matrix Model (FEM Model). Using this approach, a single model capable of simulating a complete range of focus and exposure conditions can be generated with minimal effort. Such models will be shown to achieve a predictive accuracy of less than 5nm for device patterns at nominal conditions and less than 10nm across the entire range of process conditions which define the nominal process window. Based on the inspection results of the full chip LMC check, we identify process weak points (with limited process window or excessive sensitivity to mask error) and provide feedback to the front end design stage for pattern correction to maximize the overall process window and increase production manufacturability. The performance and full function of LMC will also be described in this paper.
Obtaining good post-etching CD uniformity is getting more and more important in advanced processes such as 90 nm, 65 nm, and even 45nm for 300 mm wafers. But process noise greatly impacts the CD uniformity, especially etching bias and metrology noise. To achieve a CD uniformity of below 3 nm for 300 mm post-etch wafers, the metrology noise and process noise must be reduced and compensated for. In this paper, we demonstrate spectroscopic ellipsometry CD with the advantages of high stability and high accuracy to get CD information precisely, and high sensitivity to monitor PEB temperature and exposure energy fine variation in order to compensate for the etching bias.
This study focuses on the feasibility of minimizing the CD uniformity of post-etch wafers by ADI CD compensation for a 300 mm leading-edge fab. Because the CD uniformity of after-development inspection (ADI) wafers from a leading-edge lithographic tool could be in the range of only 3 nm, it is very challenging to reveal the true CD signature of an ADI wafer using a metrology tool. A spectroscopic ellipsometry based metrology tool, SpectraCD, was used in this study. In order to make sure the CD signatures reported by SpectraCD reveal the true behavior of a lithographic tool, the well-published Total Test Repeatability (TTR) test was adopted. In comparison with 3 nm CD uniformity, a 0.2 nm TTR is accurate enough for this study. In addition, from more than 100 wafers produced within a week, the CD signature of ADI wafers is very stable on wafer-to-wafer and lot-to-lot bases. Basically, all the ADI wafers produced from a single post-exposure-bake plate of an exposure tool within a week show very similar CD signatures. The feasibility of reaching a CD uniformity of 3 nm for post-etch wafers will be demonstrated in this study.