The semiconductor industry has adopted multi-patterning techniques to manage the delay in the extreme ultraviolet lithography technology. During the design process of double-patterning lithography layout masks, two polygons are assigned to different masks if their spacing is less than the minimum printable spacing. With these additional design constraints, it is very difficult to find experienced layout-design engineers who have a good understanding of the circuit to manually optimize the mask layers in order to minimize color-induced circuit variations. In this work, we investigate the impact of double-patterning lithography on analog circuits and provide quantitative analysis for our designers to select the optimal mask to minimize the circuit’s mismatch. To overcome the problem and improve the turn-around time, we proposed our smart “anchoring” placement technique to optimize mask decomposition for analog circuits. We have developed a software prototype that is capable of providing anchoring markers in the layout, allowing industry standard tools to perform automated color decomposition process.
At advanced and mainstream process nodes (e.g., 7nm, 14nm, 22nm, and 55nm process nodes), lithography hotspots can exist in layouts of integrated circuits even if the layouts pass design rule checking (DRC). Existence of lithography hotspots in a layout can cause manufacturability issues, which can result in yield losses of manufactured integrated circuits. In order to detect lithography hotspots existing in physical layouts, pattern matching (PM) algorithms and commercial PM tools have been developed. However, there are still needs to use DRC tools to perform PM operations. In this paper, we propose a PM synthesis methodology, which uses a continuous refinement technique, for the automatic synthesis of a given lithography hotspot pattern into a DRC deck, which consists of layer operation commands, so that an equivalent PM operation can be performed by executing the synthesized deck with the use of a DRC tool. Note that the proposed methodology can deal with not only exact patterns, but also range patterns. Also, lithography hotspot patterns containing multiple layers can be processed. Experimental results show that the proposed methodology can accurately and efficiently detect lithography hotspots in physical layouts.
As process technology scales down, the number of Chemical Mechanical Polishing (CMP) processes and steps used in chip manufacturing are increasing exponentially. Shrinking process margins increase the risk of excessive metal or oxide thickness or topography variations, causing potential yield problems such as dishing, erosion, resist lifting or printability issues.
Present DFM CMP modeling and applications mainly focus on the hotspot detection and fixing methodology for the Back-End-Of-Line (BEOL) layers . Today, the present methodology is no longer sufficient to eliminate all the CMP related manufacturing defects. There is a strong demand for STI, poly and contact silicon calibrated CMP models to predict and fix the related CMP hotspots.
Shallow Trench Isolation (STI) and Poly CMP planarity is very critical in advanced technologies with Diffusion layer FIN structures and Replacement Metal Gate Process flow . Gate uniformity after CMP will improve device performance, reduce CMP defects and increases the yield. Contact (Tungsten) CMP polishing is another important step that defines contact planarity, which will influence metal layer CMP planarization .
This paper will discuss design dependent CMP variations for STI, Poly and Contact CMP steps and showcase the importance of FEOL CMP modeling. We present the methodology for Silicon calibrated STI CMP, Poly and Contact CMP models and the applications of FEOL CMP models in CMP dishing and erosion hotspot analysis. We also present FEOL plus BEOL multi stack CMP simulations applications and provide design guidelines to fix CMP hotspots.
Proc. SPIE. 10148, Design-Process-Technology Co-optimization for Manufacturability XI
KEYWORDS: Semiconductors, Lithium, Capacitors, Databases, Metals, Error analysis, Silicon, Manufacturing, Transistors, Resistors, Analog electronics, Digital electronics, System on a chip, New and emerging technologies
Analog circuits are sensitives to the changes in the layout environment conditions, manufacturing
processes, and variations. This paper presents analog verification flow with five types of analogfocused
layout constraint checks to assist engineers in identifying any potential device mismatch and
layout drawing mistakes. Compared to several solutions, our approach only requires layout design,
which is sufficient to recognize all the matched devices. Our approach simplifies the data preparation
and allows seamless integration into the layout environment with minimum disruption to the custom
layout flow. Our user-friendly analog verification flow provides the engineer with more confident with
their layouts quality.
Proc. SPIE. 9781, Design-Process-Technology Co-optimization for Manufacturability X
KEYWORDS: Data modeling, Calibration, Etching, Metals, Copper, Silicon, Manufacturing, Design for manufacturing, Semiconducting wafers, Product engineering, Chemical mechanical planarization, Back end of line, Design for manufacturability
As we move to advanced technology nodes, the requirements on within chip and across wafer planarity are becoming more demanding . Also, the number of Chemical Mechanical Polishing (CMP) processes and steps used in microelectronic chip manufacturing is increasing rapidly, in an effort to meet the stringent planarity requirements . However, the complex pattern dependencies inherent in CMP processes, and the cumulative nature of the topography generated by these processes make it challenging to meet the aforementioned stringent uniformity requirements for the variety of designs produced. Consequently, we expect to see an increased CMP and related hotspots on advanced node designs. Accurately detecting CMP and related hotspots (such as pooling, DOF hotspots, topography variation hotspots etc.) and providing guidelines to fix or prevent them is therefore critical for CMP process development, yield ramp up and shorter design and manufacturing cycles.
In this paper we present a hotspot detection and removal/prevention flow. The flow uses Cadence Design System’s manufacturing modeling methodology that predicts feature scale, within chip, and wafer level topography. The modeling methodology takes into account etch depth, deposition, and CMP variations across multiple levels in the design, and across multiple process steps within a given design level.