A three-dimensional (3-D) 4×4×4 optical interconnect Mesh network scheme for parallel multiprocessor system based
on polymer light waveguide electro-optical printed circuit board(EOPCB) is proposed in this paper. The Mesh
topological structures of light waveguide interconnects for processor element chip-to-chip on a board, and board-toboard
on backplane is constructed. The system consists of 64 processor element chips interconnected in a 3-D Mesh
network configuration. Every processor board comprises 4x4 processor element chips with Mesh interconnection.
Board-to-board Mesh interconnects are established on a backplane through light waveguide Mesh interconnect
topological structure. An additional optical layer with light waveguide structure is used in conventional PCB to construct
EOPCB. Vertical cavity surface emitting laser (VCSEL) array is used as optical transmitter array. PIN photodiode array
is used as optical receiver array. A MT-compatible direct coupling method is presented to couple light beam between
optical transmitter/receiver with light waveguide layer. The optical signals from a processor element chip on a board can
transmit to another processor element chip on another board through light waveguide interconnection in the backplane.
So 3-D optical interconnection Mesh network for parallel multiprocessor system can be reailzed by EOPCB.
A star-based two-dimensional (2-D) torus inter-chip network on electro-optical printed circuit board (EOPCB) is
proposed to provide a simple and effective interconnection solution for such a real-time distributed parallel systems as
satellite image processing, which is characterized with locally intensive communication. The proposed hybrid
interconnection network has a hierarchical structure where the higher level is a 2-D torus network of 8×8 optical cross-connects
(OXCs) and the lower level is a cluster of processors connected in star topology using4×4OXCs. EOPCB is
used to eliminate the electrical bottleneck of high speed interconnection on board. OXCs are used to eliminate the
expensive E/O/E conversion of electrical routers and provide a transparent optical channel between processors. A new
approach based on combination network is proposed to construct 4×4 and 8×8OXCs with 2×2optical crossbars.
On-chip networks (NoCs) for future Systems-on-chips (SoCs) will be required to consume as little energy as possible while satisfying other performance constraints. Meanwhile, NoCs has to deal with the increasing sensitivity of communication links to noise sources such as crosstalk or power supply noise. We focus on the communication reliability for NoCs from an energy-efficient viewpoint. Firstly, a new framework to implement error-control schemes is proposed. No encoders are needed for the communication switches of NoCs in this framework. Secondly, we model on-chip interconnect as noisy channels and evaluate the energy-efficiency of parallel error-detection codes through the experiments on two kinds of codes: PARITY code and Hamming code. The supply voltages Vdd are analyzed to meet the predefined reliability requirements. The results show that up to 15.4% power reduction can be achieved by parallel codes and it can make an appropriate trade-off between power, delay and wires.
Greedy demand of high speed communication has made electrical interconnection on board a bottleneck. Electro-Optical Printed Circuit Board (EOPCB) was proposed to relieve the pressure by introducing an optical layer to common printed circuit board. Nowadays, most of the proposed EOPCB solutions focused on the design of optical transceiver structure and optical interconnection was used directly to replace high speed electrical interconnection by employing transceiver arrays. This approach would need many VCSEL-PIN pairs for a single high speed chip on board, thus increase the cost and also decrease the efficiency of optical interconnection. To defeat the weakness, a network approach, where only one VCSEL-PIN pair is required for a chip, is proposed in this paper. A novel Optoelectronic
integrated circuit (OEIC) architecture is introduced to make this network approach possible.
A 5 to 10 Gbps bandwidth optical interconnecting and switching network system used on parallel computing is introduced in this paper. This system provides a high bandwidth to meet the request of high bandwidth of the parallel computing. Optics is used to be a media to carry data and optical crossbar interconnection board is used to switch data in this system. It comes over the inherent disadvantage of the R, L, C delay and clock skew of the electronics interconnection. This system has good stability and scalability.