In recent years, 193nm immersion lithography has been extended instead of adopting EUV lithography. And multi-patterning technology is now widely applied, which requires tighter specification as the pattern size gets smaller on advanced semiconductor devices. Regarding the mask registration metrology, it is necessary to consider some difficult challenges like tight repeatability and complex In-Die pattern measurement. In this study, the registration measurement capability was investigated on new registration metrology tool IPRO5+, and new measurement method called Model-Based measurement was evaluated. And the performance and the prospect for advanced technology masks of the IPRO5+ were discussed based on the evaluation results.
Photomask Japan each year hosts a meeting inviting the conference attendees to actively participate in a discussion on a
selected topic. The topic selected for this year is on new mask inspection and metrology techniques that are just
emerging in the market, namely, aerial/wafer image based inspection and metrology, and optical high sampling
frequency CD uniformity measurement. The panel discussion hopes to identify potential values of each technique and
at the same time discover any challenge if the industry were to adopt such technique.
We have evaluated a unified mask pattern data format named "OASIS.MASK"1 and a unified job deck format
named "MALY"2 for mask tools as the input data formats of the inspection tool using the mask data and the photomask
produced with the 65nm design rule. The data conversion time and the data volume for the inspection data files were
evaluated by comparing with the results for using the native EB data and the native job deck data. The inspection speed
and the defect number of the inspection tool were also evaluated with the actual inspection tool. We have confirmed that
there is no large issue in applying OASIS.MASK and MALY to the input data formats of the inspection tool and they
can become the common intermediate format in our MDP flow. The detail of evaluation results will be mainly
introduced in this paper.
As part of the technical program in Photomask Japan 2007, we held a panel discussion to discuss challenges and
solutions for the double exposure and double patterning lithography technique for 32nm half-pitch design node. 4
panelists, Rik Jonckheere of IMEC (Belgium), Tsann-Binn Chiou of ASML Taiwan Ltd. (Taiwan), Judy Huckabay of
Cadence Design Systems Inc. (USA) and Yoshimitsu Okuda of Toppan Printing Co., Ltd. (Japan) were invited to
represent each key technical area.
We also took a survey from the PMJ attendees prior to the panel discussion, to vote which key technical area they think
the challenge exists for the 32nm half-pitch DE/DP lithography. The result of the survey was also presented during the
One would intuitively think that by using a DE/DP technique you're relaxing the design rule by 2x, thus for 32nm node
it's essentially the 65nm process- you're just repeating it 2 times. Well, not exactly, as identified by the panelists and
the participants in the discussion. We recognized the difficulties in the LSI fabrication process steps, the lithography
tool overlay, photomask CD and registration, and the issue of data splitting conflict.
These difficulties are big challenge for both LSI and photomask manufactures; however, we have confirmed some
solutions are already examined by the theoretical and experimental works of the people in research. Despite these
difficulties, we are convinced that the immersion lithography with double exposure and double patterning techniques is
one of the most promising candidates of the lithography for 32nm half pitch design node.
A traditional method of mask quality control in a fab has been wafer image qualification i.e., wafer inspection on printed monitor wafer or wafer inspection on production wafer. But recently many fabs that are using DUV lithography for low k1 process are experiencing the progressive defect growth challenge (such as crystal growth, haze, fungus, precipitate etc.) on their photomasks. The quality of some reticles will worsen over time due to this progressive defect problem on the mask. Hence it is important to detect such problems before they start impacting the device yield. An evaluation was constructed in a Japanese advanced logic fab to compare the performance between traditional image qualification methods and direct reticle inspection using TeraStar STARlight. The goal was to determine if the TeraStar STARlight inspection could provide the sensitivity required to give early warning of progressive defects before image qualification can detect these defects. Evaluation results show that TeraStar STARlight is the most effective method in a fab to provide early warning to a progressive defect growth on reticle that is likely to print later during mask life.
We discussed the following topics at the panel discussion of Photomask Japan 2002. 1) Pushing the limit of ArF lithography: How far ArF lithography will extend? 2) Current status and issues for F2 lithography, 3) Current status and issues for EPL, 4) Current status and issues for F2 and NGL masks, 5) Lithography tool selection from 90- to 65- nm nodes.
ArF lithography could extend to 65-nm node by using alternating phase shift masks. F2 lithography and EPL are not yet established and we need to solve many issues for practical applications. The choice of lithography tools in 65-nm node depends on devices and layers. Multiple lithography tools might be used in 65-nm node.