Mr. Yosi Vaserman Profile

Yosi Vaserman

at Tower Semiconductor Ltd

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Proceedings Article | 13 March 2009 Paper

Design ranking and analysis methodology for standard cells and full chip physical optimization

Yosi Vaserman, Eitan Shauly

Proceedings Volume 7275, 72750R (2009) https://doi.org/10.1117/12.812972

KEYWORDS: Design for manufacturing, Transistors, Structural design, Semiconducting wafers, Optical proximity correction, Silicon, High volume manufacturing, Reliability, System identification, Logic

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Device and reliability performances of Deep Sub-Micron devices depend on the physical layout and the sensitivity of this layout to the foundry process. However, layout optimization does not necessarily means layout "relaxation" for all structures. A complex design needs a "judgment" system, which will identify the "quality" of each design rule and suggest locations to be modified. Another important task is to be able quantitatively compare between layouts, designed for the same purpose (standard cells for example). In this work, we propose a "ranking" system, which analyzes the design and prioritizes the places to be modified. Our "ranking" system consists of set of rules based on the wafer foundry process. Different check rules have different impact on performance and because of that they get different priorities within the final results. Based on that, the overall design score, and the rule-priority-of-improvement are calculated. We start by presenting our ranking analysis system. Afterwards, we compare several standard cells libraries, designed by leading 3rd party IP houses. Based on the ranking results, guidelines and priority for layout modification are defined. We also discuss the impact of different DRC coding methods on the scoring values. For example, checking the overlap of M1 layer over contact by measuring the enclosure or by measuring the overlap area. Finally, we show our analysis for several similar cells as well as for a full-chip design.

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