Typical overlay metrology marks like Box-in-Box or Advanced-Imaging-Marks print surprisingly poor when exposed
with extreme off-axis-illumination. This paper analyzes the root-cause for this behavior and establishes a method how to
understand and predict the results of overlay metrology on resist. A simulation flow is presented which covers the
lithographic exposure as well as the actual inspection of the resist profiles. This flow is then used to study the impact of
scanner/process imperfections on the overlay measurements; both image-based and diffraction-based overlay metrology
are covered. This helps to gain a deeper understanding of the critical parameters in the printing and inspection of overlay
marks, and eventually develop and assess mark enhancement strategies for image-based overlay metrology such as
chopping, or assess the benefit of diffraction-based overlay metrology. In parallel to the simulations, results of wafer
exposures are presented which investigate various aspects of overlay metrology and validate our simulations.
As K1 factor for mass-production of memory devices has been decreased to almost its theoretical limit, the process
window of lithography is getting much smaller and the production yield has become more sensitive to even small
variations of the process in lithography. So it is necessary to control the process variations more tightly than ever. In
mass-production, it is very hard to extend the production capacity if the tool-to-tool variation of scanners and/or scanner
stability through time is not minimized. One of the most critical sources of variation is the illumination pupil. So it is
critical to qualify the shape of pupils in scanners to control tool-to-tool variations.
Traditionally, the pupil shape has been analyzed by using classical pupil parameters to define pupil shape, but these
basic parameters, sometimes, cannot distinguish the tool-to-tool variations. It has been found that the pupil shape can be
changed by illumination misalignment or damages in optics and theses changes can have a great effect on critical
dimension (CD), pattern profile or OPC accuracy. These imaging effects are not captured by the basic pupil parameters.
The correlation between CD and pupil parameters will become even more difficult with the introduction of more
complex (freeform) illumination pupils.
In this paper, illumination pupils were analyzed using a more sophisticated parametric pupil description (Pupil Fit
Model, PFM). And the impact of pupil shape variations on CD for critical features is investigated. The tool-to-tool
mismatching in gate layer of 4X memory device was demonstrated for an example. Also, we interpreted which
parameter is most sensitive to CD for different applications. It was found that the more sophisticated parametric pupil
description is much better compared to the traditional way of pupil control. However, our examples also show that the
tool-to-tool pupil variation and pupil variation through time of a scanner can not be adequately monitored by pupil
parameters only, The best pupil control strategy is a combination of pupil parameters and simulated CD using measured
illumination pupils or modeled pupils.
Hyper NA system has been introduced to develop sub-60nm node memory devices. Especially memory
industries including DRAM and NAND Flash business have driven much finer technology to improve
productivity. Polarization at hyper NA has been well known as important optical technology to enhance
imaging performance and also achieve very low k1 process. The source polarization on dense structure has
been used as one of the major RET techniques. The process capabilities of various layers under specific
illumination and polarization have been explored.
In this study, polarization characteristic on 40nm memory device will be analyzed. Especially, TE
(Transverse Electric) polarization and linear X-Y polarization on hyper NA ArF system will be compared and
investigated. First, IPS (Intensity in Preferred State) value will be measured with PMM (Polarization
Metrology Module) to confirm polarization characteristic of each machine before simulation. Next simulation
will be done to estimate the CD variation impact of each polarization to different illumination. Third, various
line and space pattern of DRAM and Flash device will be analyzed under different polarized condition to see
the effect of polarization on CD of actual wafer. Finally, conclusion will be made for this experiment and
future work will be discussed.
In this paper, the behavior of 40nm node memory devices with two types of polarization is presented and
the guidelines for polarization control is discussed based on the patterning performances.
The imaging performances of XY linear and TE Azimuthal polarization were compared by thin mask
approximation and rigorous 3D mask simulation. The simulations were performed for 40nm and 44nm half pitch patterns
with a hyper NA (1.35) system. Each polarization state was assumed to have a parametric DOP (degree of polarization)
value that was set to 0.95. Rotated dipole illuminators of several angles were used for the associated tilted patterns to see
the imaging impact by IPS (intensity in the preferred state of polarization) change in the process with XY linear
polarization that has a fixed angle of polarization. The difference in performance between two polarization modes were
compared by NILS and DOF margin. Additionally, the imaging quality of BIM (binary intensity mask) with polarization
beam was studied to that of att-PSM at given process conditions. Two types of available BIM masks of different
thickness were applied to simulation to understand 3D mask simulation impact on the imaging contrast and process
margin. The estimation of two-diffraction beam balance was performed to explain the imaging simulation as well. The
polarization sensitivities of NILS and CD change by DOP were found for each feature with given exposure conditions.
The main purpose of this study is to understand how much overestimation or underestimation of conventional thin mask
simulation could be combined in the process simulation by comparing rigorous 3D mask consideration.
In hyper NA system, specific illumination combined with polarization can be used as one of major RET techniques.
Polarization at high NA dry system is also regarded as important technology to bring improvement of very low k1
process. The benefits of polarization on repeated structure are very well known. However we also need to understand
the effect on random pattern in peripheral region to adopt polarization technology successfully into real devices.
Memory device such as DRAM and NAND Flash has repeated cell structure and also loose pattern in peripheral region.
In this study two kinds of polarization function will be applied to real memory devices and the polarization behavior on
various patterns in peripheral circuit will be analyzed through actual printing process using 6% attenuated PSM at ArF
high NA dry system. The printed result will be compared on random patterns through in-line metrology tool and process
guideline including OPC treatment will be discussed based on this study, especially with regard to ID bias.
A procedure for calibrating a resist model iteratively adjusts appropriate parameters until the simulations of the model match the experimental data. The tunable parameters may include the shape of the illuminator, the geometry and transmittance/phase of the mask, light source and scanner-related parameters that affect imaging quality, resist process control and most importantly the physical/chemical factors in the resist model. The resist model can be accurately calibrated by measuring critical dimensions (CD) of a focus-exposure matrix (FEM) and the technique has been demonstrated to be very successful in predicting lithographic performance. However, resist model calibration is more challenging in the low k1 (<0.3) regime because numerous uncertainties, such as mask and resist CD metrology errors, are becoming too large to be ignored. This study demonstrates a resist model calibration procedure for a 0.29 k1 process using a 6% halftone mask containing 2D brickwall patterns. The influence of different scanning electron microscopes (SEM) and their wafer metrology signal analysis algorithms on the accuracy of the resist model is evaluated. As an example of the metrology issue of the resist pattern, the treatment of a sidewall angle is demonstrated for the resist line ends where the contrast is relatively low. Additionally, the mask optical proximity correction (OPC) and corner rounding are considered in the calibration procedure that is based on captured SEM images. Accordingly, the average root-mean-square (RMS) error, which is the difference between simulated and experimental CDs, can be improved by considering the metrological issues. Moreover, a weighting method and a measured CD tolerance are proposed to handle the different CD variations of the various edge points of the wafer resist pattern. After the weighting method is implemented and the CD selection criteria applied, the RMS error can be further suppressed. Therefore, the resist CD and process window can be confidently evaluated using the accurately calibrated resist model. One of the examples simulates the sensitivity of the mask pattern error, which is helpful to specify the mask CD control.
Polarization is becoming very important technology in micro-lithography at the higher NA lithography for much smaller design. The wide and intensive studies to apply the polarization technology into lithography application have been achieved. Source polarization, mask polarization and projection lens polarization could make different printing results compared to non-polarization cases. Especially k1 factor below 0.3 needs aggressive resolution enhancement techniques. Environmental parameters such as mask CD, lens aberration, stray light, image plane deviation and resist characteristic make CD controllability worse in the very low k1 regime. The polarization technology can contribute to getting better imaging performance. This experiment is challenging k1 factor down to 0.29 with the source polarization function. The source polarization effect on real device will be shown through the simulation and actual printing process using 6% attenuated PSM. The related OPC strategy with the polarized source will also be discussed.
As the design rule of device shrinks down, it is difficult to enlarge the process window, especially DOF (Depth of Focus). It has shown good results in resolution issues with short wavelength, high NA aperture and several RET (Resolution Enhancement Technique) like special illuminator and mask techniques and so on. But it needs to be challenged for DOF process window in contact / via process having various pitch and pattern location. It is a key point in sub 100nm process development and product. It is demonstrated that focus scan method is effective for DOF improvement in contact and via layers. Focus Scan method is one of the focus drilling techniques; it is realized to tilt wafer stage so that the same point on the wafer field can be exposed in limited continual focus range using multiple focal planes through the slit of scanner tool. In this study, confirmation was inspected for simulation and wafer evaluation for focus scan effects in view of process feasibility. DOF increased over 50% with focus scan in contact mask process even though there are several issues to be solved and considered. Energy Latitude (EL) decreased a little by image contrast drop, but if we consider the process window for evolution of device, it is relatively enough for process. OPC or Bias tuning is needed for application in contact layer having various pitch and location, and overlay issues are needed to confirm for each illuminator. From these experiments, it is found that DOF margin can easily be enhanced using focus scan method. Also some fine tuning is required to adequately use this method on production devices.
One of the crucial factors to take mostly into account the development and production of 130 nm node in low k1 DRAM process is the lens aberration sensitivity control of optical lithographic tools. To meet the required specification these impact of lens aberration resulting from reducing process window caused by pattern deformation, CD uniformity, CD asymmetry, and pattern shift etc. should be understood and considered. In this study, we mainly focused on the aberration sensitivity control for the DRAM isolation layer that is very sensitive to odd components such as coma and three-foil etc. There are a few methods to do this, but the application of extreme sigma setting that is the powerful manner to improvement of asymmetric pattern and layout rotation were examined. It was confirmed that the simulated image and real patterning results for left-right CD difference came from aberrated lens are well matched. In addition, why is the extreme sigma setting more effective than standard settings was investigated with analysis of diffraction patterns on pupil filling of projection lens optics combined with Zernike coefficients phase map.
As resolution shrinks, also the demands for litho CD Uniformity are becoming tighter. In replicating the mask pattern into photoresist, a sequence of modules within the patterning cluster (coat, expose, develop, etch) is responsible for CD non-uniformity. So far, the strategy has been to make the contribution of each of these modules as small as possible. The CD Uniformity can be improved in a more efficient way by compensating the various error sources with adapted dose profiles on the scanner. An inventory is made of the requirements for this compensation mechanism. In more detail a description is given how the scanner can apply these dose corrections. With experiments, the feasibility of the concept is proven. Improvements in CD Uniformity over 5nm are demonstrated, both on test structures as well as on real device layers.
Comparative analysis of the total overlay accuracy on aluminum (Al) and chemical vapor deposition tungsten (CVD-W) was carried out as a function of the available alignment techniques over the various process conditions. In the case of Al films, they were prepared at the various sputtering temperatures, thicknesses, and step heights. The total accuracy was also examined associated with standard and off-axis illumination (OAl). The effect of the sputtering temperature of single and dual Al deposition has been especially investigated in a view of surface roughness, which significantly affects total overlay accuracy. It was observed that CVD-W film can be an alternative of Al film. As the Al film deposition temperature decreases, it was found out that random requisition error with a large distribution was improved by implementing an off-axis alignment (OAA) technique with a visual broadband light source. Meanwhile, Al thickness was not so much critical to overlay accuracy comparing with Al sputtering temperature. And also scaling error determined by asymmetric alignment mark shape was minimized according to the optimization of exposure data file. Minimum detectable step height of alignment mark was down to 300 angstrom using a sensitive alignment techniques over the Al film.