As improving device integration for the next generation, high performance and cost down are also required
accordingly in semiconductor business. Recently, significant efforts have been given on putting EUV
technology into fabrication in order to improve device integration. At the same time, 450mm wafer
manufacturing environment has been considered seriously in many ways in order to boost up the productivity.
Accordingly, 9-inch mask has been discussed in mask fabrication business recently to support 450mm wafer
manufacturing environment successfully. Although introducing 9-inch mask can be crucial for mask industry,
multi-beam technology is also expected as another influential turning point to overcome currently the most
critical issue in mask industry, electron beam writing time. No matter whether 9-inch mask or multi-beam
technology will be employed or not, mask quality and productivity will be the key factors to survive from the
device competition. In this paper, the level of facility automation in mask industry is diagnosed and analyzed
and the automation guideline is suggested for the next generation.
In the photo-lithography process, a mask is one of the most important items because CD error from its imperfection is
transferred to the CD error on the wafer. And the CD error amplification from the mask CD to the wafer CD is denoted
by Mask Error Enhancement Factor (MEEF).
As the device shrinks so fast, MEEF increases conspicuously and massive OPC is necessary to secure the target
pattern CD and the proper process margin on the wafer. Therefore the mask CD uniformity and the just mean-to-target
(MTT) are very important to minimize the CD variation on the wafer level.
In most cases, MTT and CD uniformity for a certain device are not defined exactly. What we know is that the smaller,
the better. Because just small value of MTT and CD uniformity is not the reasonable guideline for the mask fabrication
and inducing high mask cost, defining the logical MTT and CD uniformity prospect for a certain device or layer is very
As the necessity of the low k1 process increases, MTT and CD uniformity specifications become tighter and tighter.
However the proper mask specification for sub-65nm real device has not been defined yet and not been studied
considering the mask fabrication and MEEF.
In this study, MTT and CD uniformity specification of the sub-65nm real device patterns are discussed with respect to
the mask pattern linearity and MEEFs. Mask linearity is one of the typical items for the mask fabrication and strongly
related to MTT and CD uniformity. MTT and CD uniformity tolerance also follows OPC tolerance, and OPC tolerance is
directly related to the pattern layouts and MEEF. To define the mask specification for the sub-65nm device, an example
of mask linearity effect is shown; MEEFs of the critical pattern designs are calculated and compared with each other;
MTT, CD uniformity and MEEF relationship is commented.
The low-k1 lithography produces large volumes of mask data resulting in more complex optical proximity effect. It
puts heavy burden on MDP flow and affects turn around time (TAT). To solve this problem, DP (Distributed Processing) method has been introduced. Even though DP is a very powerful tool to reduce the MDP time, there still might be
unexpected pattern drop issue. In order to deal with this issue, the verification step was added in MDP flow. The present
verification method is a boolean operation using 2 machine data after converting as a same way. However this
verification method has two shortcomings. First, this method is not suitable to detect the same error caused by same
software bug. Secondly, it needs double conversion time. A new verification method should be much faster and more
accurate than the current verification method. In this paper, the new verification method will be discussed and
experimental results using the new verification method will be shown with comparing to the old verification method.