With the increased need for low power applications, designers are being forced to employ circuit optimization
methods that make tradeoffs between performance and power. In this paper, we propose a novel transistor-level
optimization method. Instead of drawing the transistor channel as a perfect rectangle, this method involves
reshaping the channel to create an optimized device that is superior in both delay and leakage to the original
device. The method exploits the unequal drive and leakage current distributions across the transistor channel to find
an optimal non-rectangular shape for the channel. In this work we apply this technique to circuit-level leakage
reduction. By replacing every transistor in a circuit with its optimally shaped counterpart, we achieve 5% savings in
leakage on average for a set of benchmark circuits, with no delay penalty. This improvement is achieved without
any additional circuit optimization iterations, and is well suited to fit into existing design flows.
Current ORC and LRC tools are not connected to design in any way. They are pure shape-based functions. A wafer-shape based power and performance signoff is desirable for RET validation as well as for "closest-to-silicon" analysis. The printed images (generated by lithography simulation) are not restricted to simple rectilinear geometries. There may be other sources of such irregularities such as Line Edge Roughness (LER). For instance, a silicon image of a transistor may not be a perfect rectangle as is assumed by all current circuit analysis tools. Existing tools and device models cannot handle complicated non-rectilinear geometries.
In this paper, we present a novel technique to model non-uniform, non-rectilinear gates as equivalent perfect rectangle gates so that they can be analyzed by SPICE-like circuit analysis tools. The effect of threshold voltage variation along the width of the device is shown to be significant and is modeled accurately. Taking this effect into account, we find the current density at every point along the device and integrate it to obtain the total current. The current thus calculated is used to obtain the effective length for the equivalent rectangular device. We show that this method is much more accurate than previously proposed approaches which neglect the location dependence of the threshold voltage.
Focus is one of the major sources of linewidth variation. CD variation caused by defocus is largely systematic after the layout is finished. In particular, dense lines "smile" through focus while isolated lines "frown" in typical Bossung plots. This well-defined systematic behavior of focus-dependent CD variation allows us to develop a self-compensating design methodology.
In this work, we propose a novel design methodology that allows explicit compensation of focus-dependent CD variation, either within a cell (<i>self-compensated cells</i>) or across cells in a critical path (<i>self-compensated design</i>). By creating <i>iso</i> and <i>dense</i> variants for each library cell, we can achieve designs that are more robust to focus variation. Optimization with a mixture of iso and dense cell variants is possible both for area and leakage power, with the latter providing an interesting complement to existing leakage reduction techniques such as dual-Vth. We implement both heuristic and Mixed-Integer Linear Programming (MILP) solution methods to address this optimization, and experimentally compare their results. Our results indicate that designing with a self-compensated cell library incurs ~12% area penalty and ~6% leakage increase over original layouts while compensating for focus-dependent CD variation (i.e., the design meets timing constraints across a large range of focus variation). We observe ~27% area penalty and ~7% leakage increase at the worst-case defocus condition using only single-pitch cells. The area penalty of circuits after using either the heuristic or MILP optimization approach is reduced to ~3% while maintaining timing. We also apply our optimizations to leakage, which traditionally shows very large variability due to its exponential relationship with gate CD. We conclude that a mixed iso/dense library combined with a sensitivity-based optimization approach yields much better area/timing/leakage tradeoffs than using a self-compensated cell library alone. Self-compensated design shows an average of 25% leakage reduction at the worst defocus condition for the benchmark designs that we have studied.