Machine learning (ML) techniques have been applied for quick optical proximity correction (OPC) processing. A key limitation of previous ML-OPC approaches lies in the fact that a layout segment is corrected while the correction result for other segments is not reflected yet. Bidirectional recurrent neural network (BRNN) model is adopted in this paper to alleviate this problem. BRNN consists of multiple neural network instances, which are serially linked through hidden layer connections in both forward- and backward-directions. Each instance corresponds to one layout segment, so BRNN processing corrects a group of nearby segments together. Two key problems are identified and addressed: mapping between layout segments and neural network instances, and network input features. In experiments, BRNN-OPC achieves 3.9nm average EPE for test M1 layout, which can be compared to 6.7nm average EPE from state-of-the-art ML-OPC method.
Multi-bit flip-ops (MBFFs) are widely used in modern circuit designs because of their lower power consumption and smaller footprint. However, conventional MBFFs have routability issues due to the dense intra-cell connections. Since many horizontal connections are populated in the typical MBFF layouts, metal-2 (M2) tracks are highly occupied inside the cell. Accordingly, routers cannot leverage the M2 tracks for inter-cell connections. The conventional MBFFs also show a limited impact on the cell area reduction. Since the cell area saving of an MBFF mainly comes from the clock driver sharing, the layouts of other ip-op modules remain almost the same. In this paper, we propose a compact MBFF with metal-less clock routing and smaller height implementation. To achieve a sparse population of M2 routing tracks, we vertically place MBFF modules and interconnect them using the poly layer. As a result, the wire length of M2 layer inside a cell is significantly reduced. We also propose the smaller cell height implementation for compact MBFF layouts. Assuming the default standard cell height of 9 tracks, we present a 6-track MBFF implementation and the glue logic which makes legal cell placement with the 9-track logic cells. Experiments with a few test circuits show that the number of routing grids having congestion overflow is reduced by 16% and 73%, on average, compared to the single-bit flip-op and conventional MBFF based designs, respectively. Total cell area is also reduced by 8% and 2%, on average, compared to the single-bit flip-op and conventional MBFF based designs, respectively.
As the minimum feature size continues to shrink down, the interconnect resistance is getting more important. The wire RC delay now often limits the overall chip performance. In this paper, we address a wire width optimization in self-aligned double patterning (SADP) process, where wire widening and double via insertion are considered simultaneously to minimize the total wire delay of timing critical paths. For each of the wires on the critical paths, the candidate directions to which we enlarge the wire is identified while design rules are taken into account. Each candidate direction is then evaluated in terms of the potential wire delay reduction. We finally select an optimal widening configuration by reducing the problem into a minimum weight independent set (MWIS), which is solved by using an integer learning programming (ILP) solver. Experiments are conducted for a few test circuits; wire resistance is reduced by 22.4%, on average, which allows the clock period to be reduced by 12.5%.
Accurate prediction of resist profile has become more important as technology node shrinks. Non-ideal resist profiles due to low image contrast and small depth of focus affect etch resistance and post-etch result. Therefore, accurate prediction of resist profile is important in lithographic hotspot verification. Standard approaches based on a single- or multiple-2D image simulation are not accurate, and rigorous resist simulation is too time consuming to apply to full-chip. We propose a new approach of resist profile modeling through machine learning (ML) technique. A position of interest are characterized by some geometric and optical parameters extracted from surroundings near the position. The parameters are then submitted to an artificial neural network (ANN) that outputs predicted value of resist height. The new resist 3D model is implemented in commercial OPC tool and demonstrated using 10nm technology metal layer.
Conventional via patterning which relies on immersion ArF (iArF) lithography and self-aligned via (SAV) becomes
challenging in sub-7nm technology. EUV lithography (EUVL) is expected to achieve smaller feature
patterning thanks to its short wave length, but edge placement error (EPE) margin remains as another bottleneck
of pitch scaling; SAV can be aligned with metal on the top but not with the bottom of the via. Literary
study shows previous work on 2D self-aligned via (2D SAV) which can be aligned with the both metals, but it
cannot extend technology scaling beyond sub-5nm whose minimum metal pitch is expected as sub-20nm due to
essential limitation of EPE margin. We propose large marginal 2D SAV which has three times large EPE margin
than normal 2D SAV for extremely shrunk technology node (e.g. sub-5nm). Large marginal 2D SAV may allow
further feature size scaling, but it requires four EUV masks. Therefore, we present two count reduction methods
and corresponding mask decompositions and pattern re-targetings. Proposed re-targeted patterns are assessed
by source mask optimization (SMO) in terms of maximum EPE and process variation band (PVB) width.
Redundant via (RV) insertion is employed to enhance via manufacturability, and has been extensively studied. Self-aligned double patterning (SADP) process, brings a new challenge to RV insertion since newly created cut for each RV insertion has to be taken care of. Specifically, when a cut for RV, which we simply call RV-cut, is formed, cut conflict may occur with nearby line-end cuts, which results in a decrease in RV candidates. We introduce cut merging to reduce the number of cut conflicts; merged cuts are processed with stitch using litho-etch-litho-etch (LELE) multi-patterning method. In this paper, we propose a new RV insertion method with cut merging in SADP for the first time. In our experiments, a simple RV insertion yields 55.3% vias to receives RVs; our proposed method that considers cut merging increases that number to 69.6% on average of test circuits.
Bidirectional cell refers to a standard cell, in which metal-1 is used for both horizontal and vertical connections. Unidirectional cell, on the other hand, assumes reserved routing, e.g. metal-1 for only horizontal and metal-2 for only vertical connections. It has been introduced to take advantage of regular metal patterns, which are easier to print and can overcome the lithography limitations in sub-32nm technology. In unidirectional cell, metal-2 is laid out following the cell placement pitch. Since metal-2 pitch is usually different from placement pitch, some within-cell metal-2 become off track. This significantly degrades metal-2 routability. We propose a unidirectional cell with floating metal-2. After initial cell placement, metal-2 segment within each cell is snapped to nearest metal-2 track and is fixed. In addition, we propose cell redesign and post-placement optimization to enhance metal-1 routability. Metal-1 connections are forced to populate in limited number of tracks, so that remaining tracks are exposed during routing. Combined with post-placement optimization, this allows many longer metal-1 tracks to be available for horizontal connection. Experiments with test circuits show that routing errors are reduced by 7% and 60% with the proposed metal-1 considerations and floating metal-2 together.
Airgap refers to a void formed in place of some inter metal dielectric (IMD). It brings about the reduction in
coupling capacitance, which may contribute to improvement in circuit performance. We introduce two problems in this context. First is to choose the layers, where airgap should be applied, in such a way that total negative slack (TNS) is minimized for a given circuit. This has been motivated by the fact that best choice of airgap layers is different for different circuits. An algorithm is proposed to solve the problem, and is assessed against a naive approach in which airgap layers are simply fixed; additional 8% TNS reduction, on average of a few test circuits, is demonstrated. In the second problem, some wires of critical paths that are on non-airgap layers are reassigned to airgap layers such that TNS is further reduced; additional 3 to 14% of TNS reduction is observed.
EUV lithography (EUVL) is rising up as a solution of sub-10nm technology node via patterning. Due to better resolution of EUVL than it of immersion ArF (iArF) lithography, multiple iArF masks can be replaced by one EUV mask. However, for 24nm by 24nm metal grid, two diagonally neighboring vias yield either contour of two holes or peanut-shape contour. Because of the large variability of the via contours, the two vias are separably patterned with two different masks. We propose to insert bridge patterns (BPs) at the middle of the diagonally neighboring vias, so that single EUV exposure can draw peanut-shape contour consistently. In this study, we also assume 2D self-aligned via (2D SAV) which can align via holes in both vertical and horizontal direction for better edge placement error margin, so unique re-targeted via patterns that is called bridged via (BV) appears. We investigate impact of BV size and BP shapes on simulated contour using source mask optimization, and popular BVs are compared in terms of probability of failure which are calculated with Monte-Carlo simulation.
Accurate prediction of etch bias has become more important as technology node shrinks. A simulation is not feasible solution in full chip level due to excessive runtime, so etch proximity correction (EPC) often relies on empirically obtained rules or models. However, simple rules alone cannot accurately correct various pattern shapes, and a few empirical parameters in model-based EPC is still not enough to achieve satisfactory OCV. We propose a new approach of etch bias modeling through machine learning (ML) technique. A segment of interest (and its surroundings) are characterized by some geometric and optical parameters, which are received by an artificial neural network (ANN), which then outputs predicted etch bias of the segment. The ANN is used as our etch bias model for new EPC, which we propose in this paper. The new etch bias model and EPC are implemented in commercial OPC tool and demonstrated using 20nm technology DRAM gate layer.
Self-aligned double patterning (SADP) has been proposed as an alternative patterning solution for sub-10nm technology because of delay of advanced lithography beyond 193nm ArF. In conventional SADP, line and space style of dummy metal fills are inserted once main design is complete. A large buffer distance is required around the main design because no further verification of main design (in presence of fills) is performed. This causes irregular pattern density, which becomes a source of process variations. We propose integrated-fill, in which main design and dummy fill insertion are performed together. This requires a change in overall design flow, which we discuss. Integrated-fill is demonstrated in M2 layer of SADP process; M2 density increases by 15.7% with 2.3% reduction in standard deviation of density distribution; metal thickness variation is also reduced by 24%. More dummy fills cause increased coupling capacitance, which however is shown to be insignificant.
<strong>Publisher’s Note</strong>: This paper, originally published on March 16th, was replaced with a corrected/revised version on March 28th. If you downloaded the original PDF but are unable to access the revision, please contact SPIE Digital Library Customer Service for assistance. <p> </p>Interconnect corners should accurately reflect the effect of misalingment in LELE double patterning process. Misalignment is usually considered separately from interconnect structure variations; this incurs too much pessimism and fails to reflect a large increase in total capacitance for asymmetric interconnect structure. We model interconnect corners by taking account of misalignment in conjunction with interconnect structure variations; we also characterize misalignment effect more accurately by handling metal pitch at both sides of a target metal independently. Identifying metal space at both sides of a target metal.
With shrinking feature size, runtime has become a limitation of model-based OPC (MB-OPC). A few machine learning-guided OPC (ML-OPC) have been studied as candidates for next-generation OPC, but they all employ too many parameters (e.g. local densities), which set their own limitations. We propose to use basis functions of polar Fourier transform (PFT) as parameters of ML-OPC. Since PFT functions are orthogonal each other and well reflect light phenomena, the number of parameters can significantly be reduced without loss of OPC accuracy. Experiments demonstrate that our new ML-OPC achieves 80% reduction in OPC time and 35% reduction in the error of predicted mask bias when compared to conventional ML-OPC.
Verification of full-chip DSA guide patterns (GPs) through simulations is not practical due to long runtime. We develop a decision function (or functions), which receives n geometry parameters of a GP as inputs and predicts whether the GP faithfully produces desired contacts (good) or not (bad). We take a few sample GPs to construct the function; DSA simulations are performed for each GP to decide whether it is good or bad, and the decision is marked in <i>n</i>-dimensional space. The hyper-plane that separates good marks and bad marks in that space is determined through machine learning process, and corresponds to our decision function. We try a single global function that can be applied to any GP types, and a series of functions in which each function is customized for different GP type; they are then compared and assessed in 10nm technology.
A small but diverse set of test patterns is essential for the optimization of lithography parameters. We selectively extract the complicated patterns that are likely to cause lithography defects from test layouts. These patterns are hierarchically classified into groups based on geometric similarity; then, a small number of patterns are chosen to represent each group. We demonstrate this approach in the synthesis of test patterns for metal layers. The total area of the resulting test patterns is only 10% of that of a set produced using a more conventional technique; the resulting hotspot library has 30% fewer patterns, and the time required to create it is cut by an order of magnitude.
Comprehensive and compact test patterns are crucial to the development of new semiconductor
technology. In particular, the random nature of routing layers tends to create many hotspots, corresponding to patterns which are difficult to predict. Conventional group of test patterns consists of parametric typical patterns and real layout clips, which contain a lot of redundancy. The paper addresses a problem of generating comprehensive yet compact group of test patterns for random routing layers. A new method of pattern extraction and classification is proposed to solve the problem.