A pattern-based methodology for optimizing Self-Aligned Double Patterning (SADP)-compliant layout designs is developed based on detecting cut-induced hotspot patterns and replacing them with pre-characterized fixing solutions. A pattern library with predetermined fixing solutions is built. A pattern-based engine searches for matching patterns in the layout designs. When a match is found, the engine opportunistically replaces the detected pattern with a pre-characterized fixing solution, preserving only the design rule check-clean replacements. The methodology is demonstrated on a 10nm routed block. A small library of fourteen patterns reduced the number of cut-induced design rule check violations by 100% and lithography hotspots by 23%.
Printing contact-like cut mask form the line end of very dense pitches is imposing a significant challenge to lithography. Various lithography options including optical multi-patterning and EUV have been considered for sub-20nm half pitch metal line cut process. Different lithography solutions of cut mask will impose different design restrictions and thus lead to different scalability of chip. In this paper, we will study routing limitations of sub-20nm half pitch metal lines cut with various optical and EUV lithography options. Key metal routing rules for each cut mask option will be derived based on study of forbidden cut mask configurations. The associated logic area impact will be derived based on real digital design.
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