Double-patterning technology (DPT) has been a primary lithography candidate of the sub-30nm technology node. The
major concern of DPT is the critical dimension (CD) skew and overlay error between 1st and 2nd patterning, which cause
the degradation of the electrical performance in terms of timing delay. In this paper, we newly develop a systematic
method to determine the DPT scheme and the proper process specification using a statistical approach in perspective of
the pattering and electrical performance. Applying the method to the bit-line layer of the sub-30nm DRAM device, we
determine the DPT scheme (i.e. either litho-etch-litho-etch (LELE) or self-aligned double pattering (SADP) to avoid the
patterning hotspots. In addition, analyzing the statistical simulation result, we provide the process specification and
exposing sequence of two masks to avoid the electrical degradation.
Overlay performance and control requirements have become crucial for achieving high yield and reducing rework process.
Increasing discrepancy between hardware solutions and overlay requirements, especially in sub-40nm dynamic random access
memory (DRAM) devices, motivates us to study process budgeting techniques and reasonable validation methods. In this paper, we
introduce a SMEM (Statistical process Margin Estimation Method) to design the DRAM cell architecture which considers critical
dimension (CD) and overlay variations in the perspectives of both cell architecture and manufacturability. We also proposed the
method to determine overlay specifications. Using the methodologies, we obtained successfully optimized sub-40 DRAM cells which
accurately estimated process tolerances and determined overlay specifications for all layers.