This paper presents a 2X/1.5X switched-capacitor charge pump for phase change memory (PCM). For a 16-bitparallelism PCM, the set/reset time is more than 100 ns, and the charge pump should output a minimum 60 mA load current. The proposed charge pump can supply 4.1 V voltage and 0-60 mA current for PCM, with an input voltage range of 2.2-3.5 V. It can also automatically change the power conversion ratio between the 2X/1.5X modes according to input voltage. For the improvement of efficiency and load transient response, an auto-adjustable output regulation scheme is employed. In this scheme, two new reference voltages are introduced and compared with output voltage. Average lasting time of the enable signal changes under different load conditions. The Enable signal then controls booster’s power transistors switching to regulate output voltage. In this way, output voltage was controlled within a permissible range. The charge pump has been designed and simulated in a 40nm CMOS process. The results show maximum power efficiency in 30 mA load current is 90.73%, and conversion ratio control increases the efficiency by 23.06% in 3 V.
The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.
An improved sense amplifier with speed-up pre-charge scheme is introduced in this paper. What’s more, in order to avoid unexpected fatal damage while reading operation, clamp voltage is adopted. Distinguished with the conventional current sense amplifier, the proposed sense amplifier shortens not only the read access time by reducing the charging time due to parasite capacitor of storage cells but also the delay time because of the RC delay on wire by using two branches of pre-charge circuit at the both ends of bit lines. The simulation result taken in SMIC 28nm process shows that, with 1Kb PCM array, the proposed sense amplifier can efficiently reduce the access time from 33.7ns to 16.5ns.