To extend the application of ArF exposure tool, CPL is one of the most powerful technologies for the resolution enhancement. From previous study, the 2nd level writing by E-Beam writer has been developed to ensure the manufacturability of CPL process. To fulfill the application of CPL Mask, we implemented this technology for 65nm DRAM patterning. First we studied the performance and characteristics of CPL mask with optimized exposure illumination setting for the desired pattern and dimension of 65nm DRAM. Then the mask data for CPL mask manufacture has been generated by modeled pattern decomposition approach together with rule and modeled OPC. This was accomplished by using an engine named MaskWeaver. For the manufacture of CPL mask, we used a binary mask and the Qz was etched for the 180 degrees phase difference. We utilized a 2nd level writing by an E-Beam writer to make the zebra pattern that was generated by the engine for the optimized patterning performance. The exposure tool we utilized for the verification of wafer patterning is an advanced 193nm exposure system. The process performance indexes such as MEEF, process window, CD uniformity were collected to show the capability of CPL process. Also, simulation and empirical data were compared to verify the performance of CPL technology. So by using an optimized CPL technology included mask data generation skill, mask making specifications, and ArF illumination optimization, we can meet the manufacture requirement of 65nm DRAM.
Mask Error Enhancement Factor(MEEF) has recently become an important topic in determining requirements of process. MEEF is the ratio of the CD range on the wafer and the expected CD range due to the mask. It indicates that mask CD errors are in effect magnified during the optical transfer to the wafer. The resolution capability of a optical system is given by Rayleigh’s criterions: Resolution=k1*λ/NA, where λ is the wavelength of the light used and NA is defined as the sine of the maximum half angle(α) of diffracted light which can enter the lens. The k1 resolution-scaling factor (k1=CD*NA/λ) is a practical measure for expressing imaging feasibility of a given optical system. It is a important parameter and direct proportion to resolution requirement. For driving critical CD dimension contraction bellow 0.11μm, lower k1 factor is needed.
In this work we use strong OAI (Quasar 90° ) to push k1 reach 0.29 by KrF exposure tool and analysis the MEEF value on 90nm generation. The simulation result shows the predicted MEEF value is close to 9 while using KrF to 90nm resolution and real MEEF value from exposuring Line/Space pattern on wafer data is 6.2. In such high MEEF process, it is very important to control mask CD accuracy. We bring up a test pattern of serial combinations with different Line/Space dimension with the same pitch size to reduce the mask array CD variation. Finally, we compare the process window (PW) between equal and nonequal Line/Space situation. The process window can be improved 18% while line width extends from 90nm to 95nm at fixed pitch 180nm.
The chromeless phase lithography (CPL) is a potential technology for low k1 optical image. For the CPL technology, we can control the local transmission rate to get optimized through pitch imaging performance. The CPL use zebra pattern to manipulate the pattern local transmission as a tri-tone structure in mask manufacturing. It needs the 2<sup>nd</sup> level writing to create the zebra pattern. The zebra pattern must be small enough not to be printed out and the 2<sup>nd</sup> writing overlay accuracy must keep within 40nm. The request is a challenge to E-beam 2<sup>nd</sup> writing function. The focus of this paper is in how to improve the overlay accuracy and get a precise pattern to form accurate pattern transmission. To fulfill this work several items have been done. To check the possibility of contamination in E-Beam chamber by the conductive layer coating we monitor the particle count in the E-Beam chamber before and after the coated blank load-unload. The conductivity of our conductive layer has been checked to eliminate the charging effect by optimizing film thickness. The dimension of alignment mark has also been optimized through experimentation. And finally we checked the PR remain to ensure sufficient process window in our etching process. To verify the performance of our process we check the 3D SEM picture. Also we use AIMs to prove the resolution improvement capability in CPL compared to the traditional methods-Binary mask and Half Tone mask. The achieved overlay accuracy and process can provide promising approach for NGL reticle manufacturing of CPL technology.