We present an optimization methodology for the template designs of subresolution contacts using directed self-assembly (DSA) with graphoepitaxy and immersion lithography. We demonstrate the flow using a 60-nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of template error enhancement factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity and evaluate optimized template designs with TEEF metrics. Our data show that source mask optimization and inverse lithography technology are critical to achieve sub-80 nm non-L0 pitches for DSA patterns using 193i.
In this paper, we present an optimization methodology for the template designs of sub-resolution contacts using directed self-assembly (DSA) with grapho-epitaxy and immersion lithography. We demonstrate the flow using a 60nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of Template Error Enhancement Factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity, and evaluate optimized template designs with TEEF metrics. Our data shows that SMO is critical to achieve sub-80nm non- L0 pitches for DSA patterns using 193i.
We present results generated using a new gauge-based Resolution Enhancement Technique (RET) Selection flow during the technology set up phase of a 3x-node NAND Flash product. As a testcase, we consider a challenging critical level for this ash product. The RET solutions include inverse lithography technology (ILT) optimized masks with sub-resolution assist features (SRAF) and companion illumination sources developed using a new pixel based Source Mask Optimization (SMO) tool that uses measurement gauges as a primary input. The flow includes verification objectives which allow tolerancing of particular measurement gauges based on lithographic criteria. Relative importance for particular gauges may also be set, to aid in down-selection from several candidate sources. The end result is a sensitive, objective score of RET performance. Using these custom-defined importance metrics, decisions on the final RET style can be made in an objective way.
Patterning scaling trends are expected to continue until at least the 5 nm node. With the introduction of EUV
now delayed until at least the 7 nm node, 193i patterning will continue mainstream use for the foreseeable
future. This scaling increases reliance on optimized OPC and illumination and imposes strict requirements on
RET solutions, which we define here as source, optics, and mask synthesis (including SRAF). Along with the
patterning requirements, any solution must be calculated efficiently. To meet these requirements, a new RET
Selection flow has been built using the Calibre platform. This flow includes SMO, Mask synthesis to further
tune the output mask, Verification, and Analysis. The entire flow is session based, allowing runs to be cloned,
queued, and compared. The flow is built on a robust GUI framework featuring persistent database integration.
The central component of the flow is a new SMO algorithm that offers improved scalability using parallel
implementation, and improved accuracy using thick mask modeling and resist models. Lithography-aware mask
manufacturability limit enforcement is possible using an integrated inverse lithography tool. This also allows
large area patterns to be included for RET benchmarking purposes. Finally, the analysis and visualization stages
of the flow allow a particular solution to be compared against other candidates using any image metric desired.
Comparison metrics can be customized for layer and customer requirements. In this paper, we will summarize
the key points of our flow, and demonstrate it using several experiments.
Scanner matching based on CD or patterning contours has been demonstrated in past works. All of these published works require extensive wafer metrology. In contrast, this work extends a previously proposed optical pattern matching method that requires little metrology by adding the component requirements and the procedure for creating an automation flow. In a test case, we matched an ASML XT:1900i using a DOE to an ASML NXT:1950i scanner using FlexRay. The matching was conducted on a 4x nm process test layer as a development vehicle for the 2x nm product nodes. The paper summarizes the before and after matching data and analysis, with future opportunities for improvements suggested.
Scribe Line Marks (SLM) printed on substrates are a standard method used by modern scanners for wafer alignment.
Light reflected from the SLM forms a diffraction pattern which is used to determine the exact position of the wafer. The
signal strength of the diffraction order needs to reach a certain threshold for the scanner to detect it. The marks are
changed as the wafers go through various processes and are buried underneath complex film stacks. These processes
and stacks can severely reduce wafer quality (WQ). Equipment manufactures recommend several variations of the SLM
to improve WQ but these variations are not effective for certain advanced processes. This paper discusses theoretical
analysis of how SLM designs affect wafer quality, addresses the challenge of self-aligned double patterning (SADP) on
SLMs and experimentally verifies results using various structures.
Scanner matching based on wafer data has proven to be successful in the past years, but its adoption into production has
been hampered by the significant time and cost overhead involved in obtaining large amounts of statistically precise
wafer CD data. In this work, we explore the possibility of optical model based scanner matching that maximizes the use
of scanner metrology and design data and minimizes the reliance on wafer CD metrology.
A case study was conducted to match an ASML ArF immersion scanner to an ArF dry scanner for a 6Xnm technology
node. We used the traditional, resist model based matching method calibrated with extensive wafer CD measurements
and derived a baseline scanner manipulator adjustment recipe. We then compared this baseline scanner-matching recipe
to two other recipes that were obtained from the new, optical model based matching method. In the following sections,
we describe the implementation of both methods, provide their predicted and actual improvements after matching, and
compare the ratio of performance to the workload of the methods. The paper concludes with a set of recommendations
on the relative merits of each method for a variety of use cases.
As the industry drives to lower k1 imaging we commonly accept the use of higher NA imaging and advanced
illumination conditions. The advent of this technology shift has given rise to very exotic pupil spread functions that
have some areas of high thermal energy density creating new modeling and control challenges. Modern scanners are
equipped with advanced lens manipulators that introduce controlled adjustments of the lens elements to counteract the
lens aberrations existing in the system. However, there are some specific non-correctable aberration modes that are
detrimental to important structures. In this paper, we introduce a methodology for minimizing the impact of aberrations
for specific designs at hand. We employ computational lithography to analyze the design being imaged, and then devise
a lens manipulator control scheme aimed at optimizing the aberration level for the specific design. The optimization
scheme does not minimize the overall aberration, but directs the aberration control to optimize the imaging performance,
such as CD control or process window, for the target design. Through computational lithography, we can identify the
aberration modes that are most detrimental to the design, and also correlations between imaging responses of
independent aberration modes. Then an optimization algorithm is applied to determine how to use the lens manipulators
to drive the aberrations modes to levels that are best for the specified imaging performance metric achievable with the
tool. We show an example where this method is applied to an aggressive memory device imaged with an advanced ArF
scanner. We demonstrate with both simulation and experimental data that this application specific tool optimization
successfully compensated for the thermal induced aberrations dynamically, improving the imaging performance
consistently through the lot.
A top challenge for Photolithographers during a process transfer involving multiple-generation scanners is tool
matching. In a more general sense, the task is to ensure that the wafer printing results in the receiving fab will match or
even exceed those of the originating fab. In this paper we report on two strategies that we developed to perform a photo
process transfer that is tailored to the scanner's capabilities. The first strategy presented describes a method to match the
CD performance of the product features on the transferred scanner. A second strategy is then presented which considers
also the down-stream process tools and seeks to optimize the process for yield. Results presented include: ASML
TWINSCAN<sup>TM</sup> XT:1700i and XT:1900i scanners 1D printing results from a line-space test reticle, parametric sensitivity
calculations for the two scanners on 1D patterns, simulation predictions for a process-optimized scanner-matching
procedure, and final wafer results on 2D production patterns. Effectiveness of the optimization strategies was then