An informal survey conducted with key customers by Photronics indicates that the time gap between technology nodes has accelerated in recent years. Previously the cycle was three years. However, between 130nm and 90nm there was less than a 2 year gap, and between 90nm and 65nm a 1.5 year gap exists. As a result, the technical challenges have increased substantially. In addition, mask costs are rising exponentially due to high capital equipment cost, a shrinking customer base, long write times and increased applications of 193nm EAPSM or AAPSM. Collaboration among EDA companies, mask houses and wafer manufacturers is now more important than ever. This paper will explore avenues for reducing mask costs, mainly in the areas of: write-time reduction through design for manufacturing (DFM), and yield improvement through specification relaxation. Our study conducted through layout vertex modeling suggests that a simple design shape such as a square versus a circle or an angled structure helps reduce shot count and write time. Shot count reduction through mask layout optimization, and advancement in new generation E-beam writers can reduce write time up to 65%. An advanced laser writer can produce those less critical E-beam layers in less than half the time of an e-beam writer. Additionally, the emerging imprint lithography brings new life and new challenges to the photomask industry with applications in many fields outside of the semiconductor industry. As immersion lithography is introduced for 45nm device production, polarization and MEEF effects due to the mask will become severe. Larger magnification not only provides benefits on CD control and MEEF, but also extends the life time of current 90nm/65nm tool sets where 45nm mask sets can be produced at a lower cost.
Several haze studies were conducted in a test environment where UV lamps and test chambers were used to simulate a wafer fab environment. This study was designed to investigate reticles experiencing different cleaning processes in a real wafer production environment. A split test was carried out to benchmark two different fabs: an 8" R & D fab and an 8" memory production fab. Reticles cleaned with UV treatment and hot DI water were exposed on ArF scanners for up to 80 hours over a period of two months. Starlight inspection before and after laser exposure confirmed no significant defect count increase after exposure. Ion chromatography (IC) results from masks cleaned on a new Steag MaskTrack cleaner suggest that hydrogenated water (H<sub>2</sub>-H<sub>2</sub>O) and ozonated water (O<sub>3</sub>-H<sub>2</sub>O) processes can further reduce the sulfate and ammonium ion residual count by 40%. UV + hot water cleaning also shows advantages in phase and transmission preservation where less than a 0.2 degree phase angle loss per clean can be achieved.
It has been demonstrated that the write time for 50keV E-beam masks is a function of layout complexity including figure count, vertex count and total line edge. This study is aimed to improve model fitting by utilizing all the variables generated from CATS. A better correlation of R<sup>2</sup> = 0.99 was achieved by including quadratic and interaction terms. The vertex model was then applied to estimate write time of various nano-imprint templates. Accuracy of the vertex model is much better than the numbers generated from E-beam tool software. A 90nm test layout was treated with a mask optimization (MO) algorithm. A 26% write time reduction was observed through shot count reduction. The advanced features of the new generation E-beam writing tool combined with mask layout optimization, allows the same level of mask cost even though the capital cost of the new tool set increased 25%.
Various sources contribute to mask haze formation including: chemical residuals from mask cleaning, out-gassing from pellicle glue/materials, and contaminants from the scanner ambient. This joint work examines cleaning techniques for haze minimization and whether or not there is haze formation after continuous laser irradiation. Masks with various designs and different cleaning techniques were tested in an ideal environment, isolated from out-gassing or other possible contaminants from the fab environment. Masks with and without patterns were subjected to 40kJ, accumulated dose, of laser radiation to simulate a wafer fab environment. Ion Chromatography (IC) and other surface analytical techniques were used to check the surface condition of masks before and after laser exposure. No haze was found on masks through transmission and IC measurements, when the test chamber was N<sub>2</sub> purged. This may suggest that new cleaning techniques have helped reduce chemical residuals on masks. It is less likely for haze to grow when masks are clean to an ionic level and when laser exposure occurs in an uncontaminated, purged environment.
This paper investigates possible solutions to intensity imbalance minimization for 65nm node application through rigorous vector simulations. It provides a strategic plan to select the right technology for AAPSM application. Technologies such as undercut, bias, combination of undercut and bias and use of a Transparent Etch Stop Layer (TESL) are compared. The study looks at the effect of through pitch, defocus, phase error and sidewall profile on space CD bias for the technologies mentioned to determine the set of conditions that would provide the best compromise between performance and manufacturability. Simulations indicate the use of TESL along with undercut would provide best compromise between manufacturability and performance. Simulation results show that performance can be improved considerably by optimizing phase target. The use of vertical side walls is sufficient if the purpose of simulation is to determine trends. For more accurate simulations it is suggested that the profile used in simulation be matched to profiles seen on manufactured AAPSM.
Mask manufacturing rules are usually determined from assumed or experimentally acquired mask-manufacturing limits. These rules are then applied during resolution enhancement data treatment to guide and/or limit pattern correction strategies. This technique can be highly reactive and may not allow a careful tradeoff between the mask making capability and the end user needs. We have explored techniques to develop mask manufacturability rules in the context of wafer lithography and device needs.
In this paper, we consider methods to improve the capture and usage of mask making information for resolution enhancement by applying a novel test mask and design, which is tied to a process modeling software. Mask manufacturing models are established from the test maks design and these models are applied to generate geometrical rules and continuous models linking the mask making capability to the lithography requirements. The analysis of mask manufacturing constraints is extended into the device domain through yield prediction tools that capture the impact of lithography variability on device performance.
We find techniques allowing a more dynamic generation of relevant mask making constraints that can optimize both yield and cycle time in the resolution ehancement process flow. Toward this, usage cases are highlighted to illustrate the interaction of specific design layouts and our mask manufacturability.
Long write times have been an industry wide concern regarding rising mask costs. The purpose of this study is to develop a simple model that can predict mask write time precisely, without an e-beam writer. With a good understanding of the trade-offs between design complexity and write time, mask makers can work with mask designers more closely to simplify design and minimize mask cost. This work compared several basic models including calculations based on write area with a fixed e-beam shot size, a software estimation with a pre-set exposure, and a mask stage settling time. Our proposed model uses a completely different approach to examine the correlation between layout complexity (vertices count, total line edge, figure, etc.) through a CATS layout segmentation and actual write time. It is found that write time is a strong function of layout figure, vertex count and total line edge. Errors between actual write time and estimated write time from the new model reduced from 7% on average on the current production software to 3%. Additionally, the new model can operate independent of the writer type and without fractured data being transferred onto a writer. Also provided are a few case studies to evaluate the interaction between write time and basic shape/OPC (optical proximity correction). Using a simple design shape and a better data snapping strategy can reduce write time up to 10 fold for applications in nano-imprint template manufacturing. Several strategies to reduce mask cost are proposed.
To accelerate the time-to-market of advanced photomasks, Photronics launched its 90nm program in spring 2003. The program included three learning cycles and a technology transfer phase. Both 90nm test masks and product masks from leading integrated device manufacturers (IDMs) and foundries were exercised through the cycles. Stringent success criteria were set based on a survey of leading customers’ requirements and the International Technology Roadmap for Semiconductors (ITRS). Hundreds of binary masks, embedded attenuated phase shift masks (EAPSMs), and alternating aperture phase shift masks (AAPSMs) were produced throughout the program. All targets were exceeded. This paper describes program success criteria, complexity of customer requirements, 90nm test vehicle design, and efforts on improving critical dimension (CD) uniformity and registration. Results in positive and negative chemically amplified resist (CAR) and tunable etching for AAPSM are shown. Details on AAPSM undercut optimization, intensity and CD imbalance are reported.
As a result of aggressive line width shrinking of semiconductor devices in the recent years, the requirements for advanced reticles are getting more and more stringent. Therefore, it is beneficial to consider increasing the reduction ratio of projection optics in order to relax the reticle tolerances. This paper discusses quantitatively the reticle, CD, DOF and overlay accuracy requirement listed in the 1999 International Technology Roadmap for Semiconductor (ITRS) roadmap. Our simulation suggests mask drawing accuracy needs to be further improved for better CD control accuracy. Increasing reduction ratio to 6x is also another way to meet the line width requirement. Productively enhancement with 6x reduction in comparison to 4x reduction ratio is also shown.
A simple technique is introduced to compare wafer flatness measured on a non-contact capacitative flatness gauge with flatness reported by a photolithography stepper. Because the capacitive gauge measures a wafer in a mechanically free state, the differences between the two types of wafer data maps represent the sets induced by the stepper. For wafers with large Total Thickness Variations (TTV), the effective stepper flatness comes close to the true metrology flatness. However, on ultra-flat wafers with very low TTVs, the stepper signature becomes more visible, which distorts the true flatness reading. Irregular wafer shape may also affect the flatness reading on the stepper due to imperfection of vacuum chucking.
Chemical mechanical planarization (CMP) is aimed at planarizing wafer surfaces in order to meet the tightening depth-of-focus requirements for advanced lithography. A simple method will be introduced which uses the site flatness requirement from the 1994 National Technology Roadmap for Semiconductors as a criterion to qualify post- CMP wafer flatness. Wafer dimensional data measured on a capacitance gauge were converted into local flatness with different site sizes according to the roadmap. The resulting site flatness was then subtracted from the required flatness threshold. The results suggest that current CMP technology improves wafer flatness from a 0.35 micrometers technology point of view. As the design rules shrink, however, more than half of the sites do not meet the 0.25 micrometers lithographic requirements even though there are flatness improvements due to CMP. Thus, much flatter wafers and more effective planarization technologies are needed to meet the challenges of next device generations.
In this paper, introductions are focused on the principle, structure and precision of the laser-cutting machine, which has been used to etch servo-grooves and preformat information for making the master optical disk.